SN74LVT125D - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN74LVT125D
Manufacturer

TI
ChipWorker Part#

CW20432846
Category

Logic Controller, Logic IC
Package

SOIC-14
Description

3.3V ABT Quadruple Bus Buffers With 3-State Outputs 14-SOIC -40℃ to 85℃
Documentation

Datasheet

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SN74LVT125D Specifications

Attribute	Attribute Value

Part Number	SN74LVT125D
Manufacturer	TI
ChipWorker Part#	CW20432846
Category	Logic Controller, Logic IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	14 Pin
Case/Package	SOIC-14
Supply Voltage (DC)	2.70V ~ 3.60V
Number of Outputs	4 Output
Output Current	64 mA
Number of Circuits	4 Circuit
Number of Channels	4 Channel
Number of Positions	14 Position
Number of Bits	1 Bit
Propagation Delay Max (tpd)	4.00 ns
Voltage Nodes	3.30 V, 2.70 V
Quiescent Current	4.5 mA
Output Current Drive	-500 µA
Output Current (Max)	64 mA
Number of Inputs	4 Input
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	2.7V ~ 3.6V
Supply Voltage (Max)	3.6 V
Supply Voltage (Min)	2.7 V
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Size-Length	8.65 mm
Size-Width	3.91 mm
Size-Height	1.58 mm
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Not Recommended for New Designs
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The SN74LVT125D is a quadruple Bus Buffer designed specifically for low-voltage (3.3V) VCC operation, but with the capability to provide a TTL interface to a 5V system environment. It features independent line drivers with 3-state outputs. Each output is in the high-impedance state when the associated output-enable (OE)\ input is high. Active bus-hold circuitry holds unused or un-driven inputs at a valid logic state. Use of pull-up/pull-down resistors with the bus-hold circuitry is not recommended. This device is fully specified for partial-power-down applications using IOFF. The IOFF circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pull-up resistor and the minimum value of the resistor is determined by the current-sinking capability of the driver.
Supports mixed-mode signal operation
IOFF Supports partial-power-down mode operation
Bus-hold data inputs eliminate the need for external pull-up resistor
Latch-up performance exceeds 500mA per JEDEC standard JESD-17
Supports unregulated battery operation down to 2.7V
<0.8V at VCC = 3.3V, TA = 25°C VOLP (output ground bounce)
Green product and no Sb/Br

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