SN74LVTH16373DGGR - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN74LVTH16373DGGR
Manufacturer

TI
ChipWorker Part#

CW4664269
Category

Latche IC
Package

TSSOP-48
Description

Latch Transparent 3-ST 16CH D-Type 48Pin TSSOP T/R Latch Transparent 3-ST 16CH D-Type 48Pin TSSOP T/R
Documentation

Datasheet

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SN74LVTH16373DGGR Specifications

Attribute	Attribute Value

Part Number	SN74LVTH16373DGGR
Manufacturer	TI
ChipWorker Part#	CW4664269
Category	Latche IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	48 Pin
Case/Package	TSSOP-48
Supply Voltage (DC)	3.30 V, 3.60 V (max)
Number of Outputs	16 Output
Output Current	64 mA
Number of Circuits	8 Circuit
Number of Positions	48 Position
Number of Bits	16 Bit
Polarity	Non-Inverting
Voltage Nodes	3.30 V, 2.70 V
Quiescent Current	5 mA
Number of Inputs	16 Input
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	2.7V ~ 3.6V
Supply Voltage (Max)	3.6 V
Supply Voltage (Min)	2.7 V
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Size-Length	12.5 mm
Size-Width	6.1 mm
Size-Height	1.15 mm
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tape & Reel (TR)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99
HK STC License	NLR

Product Description

The SN74LVTH16373DGGR is a 16-bit transparent D Latch with 3-state outputs. It is designed for low-voltage (3.3V) VCC operation, but with the capability to provide a TTL interface to a 5V system environment. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers and working registers. It can be used as two 8-bit latches or one 16-bit latch. When the LE input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs. A buffered OE\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without interface or pull-up components.
Members of the Texas Instruments Widebus™ family
State-of-the-art advanced BiCMOS technology (ABT) design
Support mixed-mode signal operation
Support unregulated battery operation down to 2.7V
Ioff and Power-up 3-state support hot insertion
Bus hold on data inputs eliminates the need for external pull-up/pull-down resistors
Distributed VCC and GND pins minimize high-speed switching noise
Flow-through architecture optimizes PCB layout
Latch-up performance exceeds 500mA per JESD 17
Green product and no Sb/Br

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