SN74LVTH573DW - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN74LVTH573DW
Manufacturer

TI
ChipWorker Part#

CW33248404
Category

Latche IC
Package

SOIC-20
Description

Latch Transparent 3-ST 8CH D-Type 20Pin SOIC Tube
Documentation

Datasheet

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SN74LVTH573DW Specifications

Attribute	Attribute Value

Part Number	SN74LVTH573DW
Manufacturer	TI
ChipWorker Part#	CW33248404
Category	Latche IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	20 Pin
Case/Package	SOIC-20
Frequency	10 MHz
Supply Voltage (DC)	2.70V ~ 3.60V
Number of Outputs	8 Output
Output Current	64 mA
Number of Circuits	8 Circuit
Number of Positions	20 Position
Number of Bits	8 Bit
Polarity	Non-Inverting
Voltage Nodes	3.30 V, 2.70 V
Quiescent Current	5 mA
Output Current Drive	-500 µA
Number of Inputs	8 Input
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	2.7V ~ 3.6V
Supply Voltage (Max)	3.6 V
Supply Voltage (Min)	2.7 V
	expand all
Size-Length	12.8 mm
Size-Width	7.52 mm
Size-Height	2.35 mm
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

description/ordering information
These octal latches are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.
The eight latches of the ’LVTH573 devices are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs.
• Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)
• Support Unregulated Battery Operation Down to 2.7 V
• Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
• Ioff and Power-Up 3-State Support Hot Insertion
• Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
• Latch-Up Performance Exceeds 500 mA Per JESD 17
• ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)

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- Carefully tested and packaged by ChipWorker
- Vacuum packed
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- Anti-vibration foam
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- Surface testing

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