SN75LVDS84ADGG - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN75LVDS84ADGG
Manufacturer

TI
ChipWorker Part#

CW8623830
Category

Interface IC, Interface Controller
Package

TSSOP-48
Description

Texas Instruments SN75LVDS84ADGG, LVDS Transmitter 21-TX TTL LVDS, 3 → 3.6V, 48Pin, TSSOP
Documentation

Datasheet

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SN75LVDS84ADGG Specifications

Attribute	Attribute Value

Part Number	SN75LVDS84ADGG
Manufacturer	TI
ChipWorker Part#	CW8623830
Category	Interface IC, Interface Controller
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	48 Pin
Case/Package	TSSOP-48
Supply Voltage (DC)	3.00V (min)
Supply Current	35.0 mA
Number of Positions	48 Position
Power Dissipation	1637 W
Data Rate	197 Mbps
Operating Temperature (Max)	70 ℃
Operating Temperature (Min)	0 ℃
Power Dissipation (Max)	1637 mW
Supply Voltage	3V ~ 3.6V
Supply Voltage (Max)	3.6 V
Supply Voltage (Min)	3 V
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Size-Length	12.5 mm
Size-Width	6.1 mm
Size-Height	1.15 mm
Operating Temperature	0℃ ~ 70℃
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The SN75LVDS84ADGG is a FlatLink™ Transmitter contains three 7-bit parallel-load serial-out shift registers and four low-voltage differential signalling (LVDS) line drivers in a single integrated circuit. These functions allow 21 bits of single-ended LVTTL data to be synchronously transmitted over 3 balanced-pair conductors for receipt by a compatible receiver, such as the SN75LVDS82 or SN75LVDS86/86A. When transmitting, data bits D0-D20 are each loaded into registers of the LVDS84A upon the falling edge. The internal PLL is frequency-locked to CLKIN and then used to unload the data registers in 7-bit slices. The three serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN. The LVDS84A requires no external components and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user(s).
21:3 Data channel compression at up to 196Mbps throughput
Suited for SVGA, XGA or SXGA data transmission from controller to display with very low EMI
Consumes less than 0.54mW when disabled
No external components required for PLL
Outputs meet or exceed the requirements of ANSI EIA/TIA-644 standard
SSC tracking capability of 3% centre spread at 50kHz modulation frequency
Improved replacement for SN75LVDS84 and NSCs DS90CF363A 3V device
31 to 75MHz Wide phase-lock input frequency range
Green product and no Sb/Br

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