TFP403PZP - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

TFP403PZP
Manufacturer

TI
ChipWorker Part#

CW15362934
Category

Interface IC, Interface Controller
Package

TQFP-100
Description

TEXAS INSTRUMENTS TFP403PZP Specialized Interface, DVI, Desktop LCD Monitors, Digital Projectors, 3V, 3.6V, TQFP, 100Pins
Documentation

Datasheet

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TFP403PZP Specifications

Attribute	Attribute Value

Part Number	TFP403PZP
Manufacturer	TI
ChipWorker Part#	CW15362934
Category	Interface IC, Interface Controller
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	100 Pin
Case/Package	TQFP-100
Supply Voltage (DC)	3.30 V, 3.60 V (max)
Supply Current	400 mA
Number of Positions	100 Position
Power Dissipation	4.3 W
Operating Temperature (Max)	70 ℃
Operating Temperature (Min)	0 ℃
Supply Voltage	3V ~ 3.6V
Supply Voltage (Max)	3.6 V
Supply Voltage (Min)	3 V
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Size-Length	14 mm
Size-Width	14 mm
Size-Height	1 mm
Operating Temperature	0℃ ~ 70℃
Product Lifecycle Status	Active
Packaging	Tray
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The TFP403PZP is a PanelBus™ DVI Receiver, flat-panel display part of a comprehensive family of end-to-end DVI 1.0 compliant solutions. Targeted primarily at desktop LCD monitors and digital projectors, the TFP403 finds applications in any design requiring high-speed digital interface. The TFP403 supports display resolutions up to 1080p and WUXGA in 24-bit true colour pixel format. It offers design flexibility to drive one or two pixels per clock, supports TFT or DSTN panels and provides an option for time staggered pixel outputs for reduced ground bounce. It combines PanelBus™ circuit innovation with TIs advanced 0.18-µm EPIC-5™ CMOS process technology.
Supports pixel rates up to 165MHz
Digital visual interface (DVI 1.0) specification compliant
Pin-for-Pin-compatible with TFP501 for simple upgrade path to HDCP2
Laser trimmed (50R) input stage for optimum fixed impedance matching
Skew tolerant up to one pixel-clock cycle
4x Over-sampling for reduced bit-error rates and better performance over longer cables
Reduced power dissipation
Reduced ground bounce using time-staggered pixel outputs
Lowest noise and best power dissipation
Advanced technology using TI 0.18µm EPIC-5™ CMOS process
Green product and no Sb/Br

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