TL16C550 - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

TL16C550
Manufacturer

TI
ChipWorker Part#

CW550611333
RoHS

Lead free / RoHS Compliant
Description

ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH AUTOFLOW CONTROL
Documentation

Datasheet

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TL16C550 Specifications

Attribute	Attribute Value

Part Number	TL16C550
Manufacturer	TI
ChipWorker Part#	CW550611333
Documentation	Datasheet
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RoHS	RoHS Compliant
Lead-Free Status	Lead Free

Product Description

description
The TL16C550A is a functional upgrade of the TL16C450 asynchronous communications element (ACE). Functionally identical to the TL16C450 on power up (character mode†), the TL16C550A can be placed in an alternate mode (FIFO) to relieve the CPU of excessive software overhead.
In this mode, internal FIFOs are activated allowing 16 bytes (plus 3 bits of error data per byte in the receiver FIFO) to be stored in both receive and transmit modes. To minimize system overhead and maximize system efficiency, all logic is on the chip. Two of the TL16C450 terminal functions (terminals 24 and 29 on the N package and terminals 27 and 32 on the FN package) have been changed to allow signalling of direct memory address (DMA) transfers.
Capable of Running With All Existing TL16C450 Software
After Reset, All Registers Are Identical to the TL16C450 Register Set
In the FIFO Mode, Transmitter and Receiver Are Each Buffered With 16-Byte FIFOs to Reduce the Number of Interrupts to the CPU
In the TL16C450 Mode, Holding and Shift Registers Eliminate the Need for Precise Synchronization Between the CPU and Serial Data
Programmable Baud Rate Generator Allows Division of Any Input Reference Clock by 1 to (216–1) and Generates an Internal 16×Clock
Standard Asynchronous Communication Bits (Start, Stop, and Parity) Added to or Deleted From the Serial Data Stream
Independent Receiver Clock Input
Transmit, Receive, Line Status, and Data Set Interrupts Independently Controlled
Fully Programmable Serial Interface Characteristics:
– 5-, 6-, 7-, or 8-Bit Characters
– Even-, Odd-, or No-Parity Bit Generation and Detection
– 1-, 1 1/2-, or 2-Stop Bit Generation
– Baud Generation (dc to 256 Kbit/s)
False-Start Bit Detection
Complete Status Reporting Capabilities
3-State TTL Drive Capabilities for
Bidirectional Data Bus and Control Bus
Line Break Generation and Detection
Internal Diagnostic Capabilities:
– Loopback Controls for Communications Link Fault Isolation
– Break, Parity, Overrun, Framing Error Simulation
Fully Prioritized Interrupt System Controls
Modem Control Functions (CTS, RTS, DSR, DTR, RI, and DCD)
Faster Plug-In Replacement for National Semiconductor NS16550A

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