TL16C554FN - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

TL16C554FN
Manufacturer

TI
ChipWorker Part#

CW8531604
Category

UART Chip, UART Interface IC
Package

PLCC-68
Description

UART 4CH 16Byte FIFO 5V 68Pin PLCC Tube UART 4CH 16Byte FIFO 5V 68Pin PLCC Tube
Documentation

Datasheet

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TL16C554FN Specifications

Attribute	Attribute Value

Part Number	TL16C554FN
Manufacturer	TI
ChipWorker Part#	CW8531604
Category	UART Chip, UART Interface IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	68 Pin
Case/Package	PLCC-68
Supply Voltage (DC)	4.75V (min)
Voltage Rating (DC)	5.00 V
Operating Voltage	5.00 V
Supply Current	50 mA
Number of Circuits	4 Circuit
Number of Channels	4 Channel
Number of Positions	68 Position
Clock Speed	8 MHz
Power Dissipation	500 mW
Data Rate	1.00 Mbps
Operating Temperature (Max)	125 ℃
Operating Temperature (Min)	-55 ℃
Power Dissipation (Max)	500 mW
Supply Voltage	4.75V ~ 5.25V
Supply Voltage (Max)	5.25 V
Supply Voltage (Min)	4.75 V
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Size-Length	24.23 mm
Size-Width	24.23 mm
Size-Height	4.06 mm
Operating Temperature	-55℃ ~ 125℃
Product Lifecycle Status	Active
Packaging	Each
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The TL16C554FN is an Asynchronous Communications Element features that each channel performs serial-to-parallel conversion on data characters received from peripheral devices or modems and parallel-to-serial conversion on data characters transmitted by the CPU. The complete status of each channel of the quadruple ACE can be read at any time during functional operation by the CPU. The information obtained includes the type and condition of the operation performed and any error conditions encountered. The quadruple ACE can be placed in an alternate FIFO mode, which activates the internal FIFOs to allow 16 bytes (plus three bits of error data per byte in the receiver FIFO) to be stored in both receive and transmit modes. To minimize system overhead and maximize system efficiency, all logic is on the chip. Two terminal functions allow signalling of direct memory access (DMA) transfers.
False start bit detection
Complete status reporting capabilities
Line break detection and generation
Loopback controls for communications link fault isolation
Break, parity, overrun and framing-error simulation
Fully prioritized interrupt system controls
3-state Outputs provide TTL drive capabilities for bidirectional data bus and control bus
Consists of four improved TL16C550 ACEs plus steering logic
Adds or deletes standard asynchronous communication bits to or from the serial-data stream
Up to 16-MHz clock rate for up to 1-Mbaud operation
Green product and no Sb/Br

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