TLK1201AIRCP - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

TLK1201AIRCP
Manufacturer

TI
ChipWorker Part#

CW84468107
Category

Interface IC, Interface Controller
Package

HVQFP-64
Description

TEXAS INSTRUMENTS TLK1201AIRCP Ethernet Controller, 1.3Gbps, 2.3V, 2.7V, 64Pins
Documentation

Datasheet

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TLK1201AIRCP Specifications

Attribute	Attribute Value

Part Number	TLK1201AIRCP
Manufacturer	TI
ChipWorker Part#	CW84468107
Category	Interface IC, Interface Controller
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	64 Pin
Case/Package	HVQFP-64
Supply Voltage (DC)	2.50 V
Supply Current	90 mA
Number of Channels	1 Channel
Power Dissipation	2890 mW
Data Rate	1.30 Gbps
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Power Dissipation (Max)	2890 mW
Supply Voltage	2.3V ~ 2.7V
Supply Voltage (Max)	2.7 V
Supply Voltage (Min)	2.3 V
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Size-Width	10 mm
Size-Height	0.8 mm
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tray
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15

Product Description

The TLK1201A/TLK1201AI gigabit ethernet transceiver provides for ultrahigh-speed, full-duplex, point-to-point data transmissions. This device is based on the timing requirements of the 10-bit interface specification by the IEEE 802.3 gigabit ethernet specification and is also compliant with the ANSI X3.230-1994 (FC-PH) fibre channel standard. The device supports data rates from 0.6 Gbps to 1.3 Gbps.
The primary application of the transceiver is to provide building blocks for point-to-point baseband data transmission over controlled impedance media of 50 . The transmission media can be printed-circuit board traces, copper cables, or fiber-optical media. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment.
The transceiver performs the data serialization, deserialization, and clock extraction functions for a physical layer interface device. The transceiver operates at 1.25 Gbps (typical), providing up to 1 Gbps of data bandwidth over a copper or optical media interface.
The transceiver supports both the defined 10-bit interface (TBI) and a reduced 5-bit interface utilizing double data rate (DDR) clocking. In the TBI mode the serializer/deserializer (SERDES) accepts 10-bit wide 8b/10b parallel encoded data bytes. The parallel data bytes are serialized and transmitted differentially at PECL compatible voltage levels. The SERDES extracts clock information from the input serial stream and deserializes the data, outputting a parallel 10-bit data byte.
In the DDR mode the parallel interface accepts 5-bit wide 8b/10b encoded data aligned on both the rising and falling edges of the reference clock. The data is clocked most significant bit first (bits 0-4 of the 8b/10b encoded data) on the rising edge of the clock and the least significant bits (bits 5-9 of the 8b/10b encoded data) are clocked on the falling edge of the clock.
The transceiver provides a comprehensive series of built-in tests for self-test purposes including loopback and pseudorandom binary sequence (PRBS) generation and verification. An IEEE 1149.1 JTAG port is also supported.
The transceiver is housed in a high-performance, thermally enhanced, 64-pin VQFP PowerPAD package. Use of the PowerPAD package does not require any special considerations except to note that the PowerPAD, which is an exposed die pad on the bottom of the device, is a metallic thermal and electrical conductor. It is recommended that the device PowerPAD be soldered to the thermal land on the board.
The transceiver is characterized for operation from 0°C to 70°C (TLK1201A) or -40°C to 85°C (TLK1201AI).
The transceiver uses a 2.5-V supply. The I/O section is 3.3-V compatible. With a 2.5-V supply the chipset is very power-efficient, dissipating less than 200 mW typical power when operating at 1.25 Gbps.
The transceiver is designed to be hot plug capable. A power-on reset causes RBC0, RBC1, the parallel output signal terminals, TXP, and TXN to be held in a high-impedance state.

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