TMS320C5515AZCHA12 - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

TMS320C5515AZCHA12
Manufacturer

TI
ChipWorker Part#

CW8009096
Category

DSP, Digital Signal Processor
Package

LFBGA-196
Description

DSP Fixed-Point 32Bit 120MHz 240MIPS 196Pin NFBGA
Documentation

Datasheet

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TMS320C5515AZCHA12 Specifications

Attribute	Attribute Value

Part Number	TMS320C5515AZCHA12
Manufacturer	TI
ChipWorker Part#	CW8009096
Category	DSP, Digital Signal Processor
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	196 Pin
Case/Package	LFBGA-196
Frequency	120 MHz
Number of Positions	196 Position
Clock Speed	120 MHz
RAM Memory Size	320 KB
Number of Bits	16 Bit
Number of UARTs	1 UART
Number of ADCs	1 ADC
Number of Inputs and Outputs	26 Input IO
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
	expand all
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Cut Tape (CT)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	3A991.a.2

Product Description

The TMS320C5515AZCHA12 is a Digital Signal Processor (DSP) designed for low-power applications. The fixed-point DSP is based on the TMS320C55x™ DSP generation CPU processor core. The C55x™ DSP architecture achieves high performance and low power through increased parallelism and total focus on power savings. The CPU supports an internal bus structure that is composed of one program bus, one 32-bit data read bus and two 16-bit data read buses, two 16-bit data write buses and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to four 16-bit data reads and two 16-bit data writes in a single cycle. The device also includes four DMA controllers, each with 4 channels, providing data movement for 16-independent channel contexts without CPU intervention. Each DMA controller can perform one 32-bit data transfer per cycle, in parallel and independent of the CPU activity.
Low-power S/W programmable phase-locked loop (PLL) clock generator
Four core isolated power supply domains
LCD Bridge with asynchronous interface
Tightly-coupled FFT hardware accelerator
10-bit 4-Input successive approximation (SAR) ADC
Real-time clock (RTC) with crystal input, with separate clock domain and power supply
Two multimedia card/secure digital (MMC/SD) interfaces
Universal asynchronous receiver/transmitter (UART)
Serial-port interface (SPI) with four chip-selects
Master/slave inter-integrated circuit (I²C Bus™)
Four inter-IC sound (I²S Bus™) for data transport
Three internal data/operand read buses and two internal data/operand write buses
High-performance, low-power, TMS320C55x™ fixed-point digital signal processor
Green product and no Sb/Br

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