TMS320C5517AZCHA20 - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

TMS320C5517AZCHA20
Manufacturer

TI
ChipWorker Part#

CW6312196
Category

DSP, Digital Signal Processor
Package

LFBGA-196
Description

DSP Fixed-Point 16Bit 200MHz 196Pin NFBGA
Documentation

Datasheet

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TMS320C5517AZCHA20 Specifications

Attribute	Attribute Value

Part Number	TMS320C5517AZCHA20
Manufacturer	TI
ChipWorker Part#	CW6312196
Category	DSP, Digital Signal Processor
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	196 Pin
Case/Package	LFBGA-196
Frequency	200 MHz
Number of Positions	196 Position
RAM Memory Size	320 KB
Number of Bits	16 Bit
Number of UARTs	1 UART
Number of Inputs and Outputs	26 Input IO
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
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Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Cut Tape (CT)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	3A991.a.2

Product Description

The TMS320C5517AZCHA20 is a Digital Signal Processor designed for low active and standby power consumption. The device is based on the TMS320C55x DSP generation CPU processor core. The C55x DSP architecture achieves high performance and low power through increased parallelism and total focus on power savings. The CPU supports an internal bus structure that is composed of one program bus, one 32-bit data read bus and two 16-bit data read buses, two 16-bit data write buses and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to four 16-bit data reads and two 16-bit data writes in a single cycle. The device also includes four DMA controllers, each with 4 channels, providing data movement for 16 independent channel contexts without CPU intervention. Each DMA controller can perform one 32-bit data transfer per cycle, in parallel and independent of the CPU activity.
One or two instructions executed per cycle
Two arithmetic and logic units (ALUs)
Three internal data or operand read buses and two write buses
Software-compatible with C55x Devices
Tightly coupled FFT hardware accelerator
One universal host-port interface (UHPI) with 16-bit muxed address or data bus
Master and slave multichannel serial ports interface (McSPI) with three chip selects
Master and slave multichannel buffered serial ports interface (McBSP)
Universal asynchronous receiver/transmitter (UART)
Direct memory access (DMA) controller serial port interface (SPI) with four chip selects
Master and slave inter-integrated circuit (I²C Bus)
Three inter-IC sound (I²S bus) modules for data transport
Four core isolated power supply domains - Analogue, RTC, CPU and peripherals and USB
Green product and no Sb/Br

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- Vacuum packed
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