TMS320C6657CZH - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

TMS320C6657CZH
Manufacturer

TI
ChipWorker Part#

CW19245766
Category

DSP, Digital Signal Processor
Package

FCBGA-625
Description

DSP Fixed-Point/Floating-Point 16Bit 1GHz 8000MIPS 625Pin BGA
Documentation

Datasheet

TMS320C6657CZH Global Supplier

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TMS320C6657CZH Specifications

Attribute	Attribute Value

Part Number	TMS320C6657CZH
Manufacturer	TI
ChipWorker Part#	CW19245766
Category	DSP, Digital Signal Processor
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	625 Pin
Case/Package	FCBGA-625
Frequency	1 GHz
Number of Positions	625 Position
RAM Memory Size	1 MB
Number of Bits	16 Bit
Number of UARTs	2 UART
Number of Inputs and Outputs	32 Input IO
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	0 ℃
Supply Voltage (Max)	1.1 V
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Size-Length	21.1 mm
Size-Width	21.1 mm
Size-Height	2.54 mm
Operating Temperature	0℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tray
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	5A991.b.1
HK STC License	NLR

Product Description

The TMS320C6657CZH is a Digital Signal Processor provides a high performance structure for integrating RISC and DSP cores with application specific coprocessors and I/O. KeyStone is the first of its kind that provides adequate internal bandwidth for non-blocking access to all processing cores, peripherals, coprocessors and I/O. This is achieved with four main hardware elements - multicore navigator, TeraNet, multicore shared memory controller and HyperLink. Multicore navigator is an innovative packet-based manager that controls 8192 queues. When tasks are allocated to the queues, multicore navigator provides hardware-accelerated dispatch that directs tasks to the appropriate available hardware. The packet-based system on a chip (SoC) uses the two Tbps capacity of the TeraNet switched central resource to move packets.
Multicore shared memory controller (MSMC)
Memory protection unit for both MSM SRAM and DDR3_EMIF
8192 Multipurpose hardware queues with queue manager
Two Viterbi coprocessors
One Turbo coprocessor decoder
Supports direct I/O, message passing
Single port supporting 1 or 2 lanes
Supports up to 5GBaud per lane
Gigabit Ethernet (GbE) subsystem
Two multichannel buffered serial ports
Supports connections to other KeyStone architecture devices providing resource scalability
Green product and no Sb/Br

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- Carefully tested and packaged by ChipWorker
- Vacuum packed
- Anti-static packaging
- Anti-vibration foam
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- Authorities test the chip to ensure the quality, authenticity and safety of your device.
- Decapsulation control
- X-ray inspection
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- Electrical testing
- Surface testing

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