TMS320C6713BPYP200 - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

TMS320C6713BPYP200
Manufacturer

TI
ChipWorker Part#

CW13823103
Category

DSP, Digital Signal Processor
Package

LQFP-208
Description

DSP Floating-Point 32Bit 200MHz 1600MIPS 208Pin HLQFP EP
Documentation

Datasheet

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TMS320C6713BPYP200 Specifications

Attribute	Attribute Value

Part Number	TMS320C6713BPYP200
Manufacturer	TI
ChipWorker Part#	CW13823103
Category	DSP, Digital Signal Processor
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	208 Pin
Case/Package	LQFP-208
Frequency	200 MHz
Supply Voltage (DC)	1.20 V
Number of Positions	208 Position
Clock Speed	200 MHz
RAM Memory Size	264 kB
Number of Bits	32, 64 Bit
Number of I/O Pins	16 IO
Number of Inputs and Outputs	16 Input IO
Operating Temperature (Max)	90 ℃
Operating Temperature (Min)	0 ℃
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Size-Length	28.05 mm
Size-Width	28.05 mm
Size-Height	1.45 mm
Operating Temperature	0℃ ~ 90℃
Product Lifecycle Status	Active
Packaging	Tray
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15

Product Description

The TMS320C67x DSPs (including the TMS320C6713B device) compose the floating-point DSP generation in the TMS320C6000 DSP platform. The C6713B device is based on the high-performance, advanced very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making this DSP an excellent choice for multichannel and multifunction applications.
Operating at 225 MHz, the C6713B delivers up to 1350 million floating-point operations per second (MFLOPS), 1800 million instructions per second (MIPS), and with dual fixed-/floating-point multipliers up to 450 million multiply-accumulate operations per second (MMACS).
Operating at 300 MHz, the C6713B delivers up to 1800 million floating-point operations per second (MFLOPS), 2400 million instructions per second (MIPS), and with dual fixed-/floating-point multipliers up to 600 million multiply-accumulate operations per second (MMACS).
The C6713B uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 4K-byte direct-mapped cache and the Level 1 data cache (L1D) is a 4K-byte 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 256K-byte memory space that is shared between program and data space. 64K bytes of the 256K bytes in L2 memory can be configured as mapped memory, cache, or combinations of the two. The remaining 192K bytes in L2 serves as mapped SRAM.
The C6713B has a rich peripheral set that includes two Multichannel Audio Serial Ports (McASPs), two Multichannel Buffered Serial Ports (McBSPs), two Inter-Integrated Circuit (I2C) buses, one dedicated General-Purpose Input/Output (GPIO) module, two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM, SBSRAM, and asynchronous peripherals.
The two McASP interface modules each support one transmit and one receive clock zone. Each of the McASP has eight serial data pins which can be individually allocated to any of the two zones. The serial port supports time-division multiplexing on each pin from 2 to 32 time slots. The C6713B has sufficient bandwidth to support all 16 serial data pins transmitting a 192 kHz stereo signal. Serial data in each zone may be transmitted and received on multiple serial data pins simultaneously and formatted in a multitude of variations on the Philips Inter-IC Sound (I2S) format.
In addition, the McASP transmitter may be programmed to output multiple S/PDIF, IEC60958, AES-3, CP-430 encoded data channels simultaneously, with a single RAM containing the full implementation of user data and channel status fields.
The McASP also provides extensive error-checking and recovery features, such as the bad clock detection circuit for each high-frequency master clock which verifies that the master clock is within a programmed frequency range.
The two I2C ports on the TMS320C6713B allow the DSP to easily control peripheral devices and communicate with a host processor. In addition, the standard multichannel buffered serial port (McBSP) may be used to communicate with serial peripheral interface (SPI) mode peripheral devices.
The TMS320C6713B device has two bootmodes: from the HPI or from external asynchronous ROM. For more detailed information, see the _bootmode_ section of this data sheet.
The TMS320C67x DSP generation is supported by the TI eXpressDSP set of industry benchmark development tools, including a highly optimizing C/C++ Compiler, the Code Composer Studio Integrated Development Environment (IDE), JTAG-based emulation and real-time debugging, and the DSP/BIOS kernel.

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