TMS320C6745DPTPA3 - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

TMS320C6745DPTPA3
Manufacturer

TI
ChipWorker Part#

CW9574255
Category

DSP, Digital Signal Processor
Package

LQFP-176
Description

DSP Fixed-Point/Floating-Point 32Bit 375MHz/456MHz 3648MIPS 176Pin HLQFP
Documentation

Datasheet

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TMS320C6745DPTPA3 Specifications

Attribute	Attribute Value

Part Number	TMS320C6745DPTPA3
Manufacturer	TI
ChipWorker Part#	CW9574255
Category	DSP, Digital Signal Processor
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	176 Pin
Case/Package	LQFP-176
Frequency	375 GHz
Clock Speed	375 GHz
RAM Memory Size	320 KB
Number of UARTs	3 UART
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
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Operating Temperature	-40℃ ~ 105℃ (TJ)
Product Lifecycle Status	Active
Packaging	Tray
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
ECCN Code	3A991.a.2

Product Description

The TMS320C6745/6747 device is a low-power digital signal processor based on a TMS320C674x DSP core. It consumes significantly lower power than other members of the TMS320C6000 platform of DSPs.
The TMS320C6745/6747 device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices featuring high processing performance .
The TMS320C6745/6747 DSP core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 32-KB direct mapped cache and the Level 1 data cache (L1D) is a 32-KB 2-way set-associative cache. The Level 2 program cache (L2P) consists of a 256-KB memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. Although the DSP L2 is accessible by other hosts in the system, an additional 128KB of RAM shared memory (TMS320C6747 only) is available for use by other hosts without affecting DSP performance.
The peripheral set includes: a 10/100 Mbps Ethernet MAC (EMAC) with a management data input/output (MDIO) module; two I2C Bus interfaces; 3 multichannel audio serial ports (McASPs) with 16/9 serializers and FIFO buffers; two 64-bit general-purpose timers each configurable (one configurable as watchdog); a configurable 16-bit host-port interface (HPI) [TMS320C6747 only]; up to 8 banks of 16 pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 3 UART interfaces (one with both RTS and CTS); three enhanced high-resolution pulse width modulator (eHRPWM) peripherals; three 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 auxiliary pulse width modulator (APWM) outputs; two 32-bit enhanced quadrature encoded pulse (eQEP) peripherals; and 2 external memory interfaces: an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals, and a higher speed memory interface (EMIFB) for SDRAM.
The Ethernet Media Access Controller (EMAC) provides an efficient interface between the TMS320C6745/6747 device and the network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbps and 100 Mbps in either half- or full-duplex mode. Additionally, an MDIO interface is available for PHY configuration.
The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.

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