TMS320C6748BZWT4 - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

TMS320C6748BZWT4
Manufacturer

TI
ChipWorker Part#

CW44508610
Category

DSP, Digital Signal Processor
Package

LFBGA-361
Description

DSP Fixed-Point/Floating-Point 64Bit 456MHz 3648MIPS 361Pin NFBGA
Documentation

Datasheet

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TMS320C6748BZWT4 Specifications

Attribute	Attribute Value

Part Number	TMS320C6748BZWT4
Manufacturer	TI
ChipWorker Part#	CW44508610
Category	DSP, Digital Signal Processor
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	361 Pin
Case/Package	LFBGA-361
Frequency	456 MHz
Supply Voltage (DC)	1.25V (min)
Number of Positions	361 Position
Clock Speed	375456 MHz
RAM Memory Size	256 kB
Number of Bits	32 Bit
Number of UARTs	3 UART
Number of Inputs and Outputs	144 Input IO
Operating Temperature (Max)	90 ℃
Operating Temperature (Min)	0 ℃
Number of DACs	1 DAC
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Size-Length	16.1 mm
Size-Width	16.1 mm
Size-Height	0.95 mm
Operating Temperature	0℃ ~ 90℃
Product Lifecycle Status	Obsolete
Packaging	Each
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15

Product Description

The TMS320C6748BZWT4 is a fixed/floating-point Digital Signal Processor provides significantly lower power than other members of the TMS320C6000™ platform of DSPs. The device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices with robust operating systems, rich user interfaces and high processor performance through the maximum flexibility of a fully integrated, mixed processor solution. The device DSP core uses a 2-level cache-based architecture. The level 1 program cache (L1P) is a 32kB direct mapped cache and the level 1 data cache is a 32kB 2-way, set-associative cache. The level 2 program cache consists of a 256kB memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache or combinations of the two. Although the DSP L2 is accessible by other hosts in the system, an additional 128kB of RAM shared memory.
Dedicated 16-bit time-based counter with period and frequency control
6 Single-edge outputs, 6 dual-edge symmetric outputs or 3 dual-edge asymmetric outputs
Dead-band generation
PWM Chopping by high-frequency carrier
High-speed parallel interface to FPGAs and data converters
Data width on both channels is 8- to 16-bit inclusive
Single-data rate or dual-data rate transfers
Supports multiple interfaces with START, ENABLE and WAIT controls
Two multichannel buffered serial ports (McBSPs)
One multichannel audio serial port (McASP)
Dedicated interrupt controller
Dedicated switched central resource
Standard power-management mechanism
Two multimedia card (MMC)/secure digital (SD) card interfaces with secure data I/O (SDIO) interfaces
Hardware support for modulo loop operation
Exceptions support for error detection and program redirection

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