TMS320C6748BZWTA3 - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

TMS320C6748BZWTA3
Manufacturer

TI
ChipWorker Part#

CW92463590
Category

DSP, Digital Signal Processor
Package

NFBGA-361
Description

DSP Fixed-Point/Floating-Point 64Bit 375MHz 3000MIPS 361Pin NFBGA
Documentation

Datasheet

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TMS320C6748BZWTA3 Specifications

Attribute	Attribute Value

Part Number	TMS320C6748BZWTA3
Manufacturer	TI
ChipWorker Part#	CW92463590
Category	DSP, Digital Signal Processor
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	361 Pin
Case/Package	NFBGA-361
Frequency	375 MHz
Supply Voltage (DC)	1.80V (min)
Number of Positions	361 Position
Clock Speed	375456 MHz
RAM Memory Size	128 KB
Number of Bits	16 Bit
Number of UARTs	3 UART
Number of Inputs and Outputs	144 Input IO
Operating Temperature (Max)	105 ℃
Operating Temperature (Min)	-40 ℃
Number of DACs	1 DAC
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Size-Height	0.95 mm
Operating Temperature	-40℃ ~ 105℃ (TJ)
Product Lifecycle Status	Obsolete
Packaging	Each
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15

Product Description

The TMS320C6748BZWTA3 is a Fixed/Floating Point Digital Signal Processor, low-power applications processor based on a C674x DSP core. This DSP provides significantly lower power than other members of the TMS320C6000™ platform of DSPs. The device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices with robust operating systems, rich user interfaces and high processor performance through the maximum flexibility of a fully integrated, mixed processor solution. The device DSP core uses a 2-level cache-based architecture. The level 1 program cache (L1P) is a 32kB direct mapped cache and the level 1 data cache (L1D) is a 32kB 2-way, set-associative cache. The level 2 program cache (L2P) consists of a 256kB memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache or combinations of the two.
375 and 456MHz C674x fixed- and floating-point VLIW DSP
Enhanced Direct Memory Access Controller 3 (EDMA3)
Load-store architecture with nonaligned support
64 General-purpose registers (32-bit)
Six ALU (32- and 40-bit) functional units
Supports TI DSPBIOS and chip support library and DSP library
128kB RAM shared memory
LCD controller
Two serial peripheral interfaces (SPIs) each with multiple chip selects
Two multimedia card (MMC)/secure digital (SD) card interfaces with secure data I/O (SDIO) interfaces
Two master and slave inter-integrated circuits (I²C bus)
One host-port interface (HPI) with 16-bit wide muxed address and data bus for high bandwidth
Programmable real-time unit subsystem (PRUSS)
Standard power-management mechanism
USB 1.1 OHCI (host) with integrated PHY (USB1)
USB 2.0 OTG port with integrated PHY (USB0)
Real-time clock (RTC) with 32kHz oscillator and separate power rail
Three 64-bit general-purpose timers (each configurable as two 32-bit timers)
One 64-bit general-purpose or watchdog timer (configurable as two 32-bit general-purpose timers)
Two enhanced high-resolution pulse width modulators (eHRPWMs)
IC can be damaged by ESD. We recommend that all ICs be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

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