TMS320DM642AZDK6 - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

TMS320DM642AZDK6
Manufacturer

TI
ChipWorker Part#

CW28428703
Category

DSP, Digital Signal Processor
Package

FCBGA-548
Description

DSP Fixed-Point 32Bit 600MHz 4800MIPS 548Pin FCBGA
Documentation

Datasheet

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TMS320DM642AZDK6 Specifications

Attribute	Attribute Value

Part Number	TMS320DM642AZDK6
Manufacturer	TI
ChipWorker Part#	CW28428703
Category	DSP, Digital Signal Processor
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	548 Pin
Case/Package	FCBGA-548
Frequency	600 MHz
Supply Voltage (DC)	3.14V (min)
Clock Speed	720 MHz
RAM Memory Size	160 kB
Number of Bits	64 Bit
Operating Temperature (Max)	90 ℃
Operating Temperature (Min)	0 ℃
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Operating Temperature	0℃ ~ 90℃
Product Lifecycle Status	Not Recommended for New Designs
Packaging	Tray
RoHS	Non-Compliant
Lead-Free Status	Contains Lead
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	3A991.a.2
HK STC License	NLR

Product Description

* High-Performance Digital Media Processor (TMS320DM642) * 2-, 1.67-, 1.39-ns Instruction Cycle Time * 500-, 600-, 720-MHz Clock Rate * Eight 32-Bit Instructions/Cycle * 4000, 4800, 5760 MIPS * Fully Software-Compatible With C64x™ * VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word VLIW) TMS320C64x™ DSP Core * Eight Highly Independent Functional Units With VelociTI.2™ Extensions: * Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle * Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle * Load-Store Architecture With Non-Aligned Support * 64 32-Bit General-Purpose Registers * Instruction Packing Reduces Code Size * All Instructions Conditional * Instruction Set Features * Byte-Addressable (8-/16-/32-/64-Bit Data) * 8-Bit Overflow Protection * Bit-Field Extract, Set, Clear * Normalization, Saturation, Bit-Counting * VelociTI.2™ Increased Orthogonality * L1/L2 Memory Architecture * 128K-Bit (16K-Byte) L1P Program Cache (Direct Mapped) * 128K-Bit (16K-Byte) L1D Data Cache (2-Way Set-Associative) * 2M-Bit (256K-Byte) L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation) * Endianess: Little Endian, Big Endian * 64-Bit External Memory Interface (EMIF) * Glueless Interface to Asynchronous Memories (SRAM and EPROM) and Synchronous Memories (SDRAM, SBSRAM, ZBT SRAM, and FIFO) * 1024M-Byte Total Addressable External Memory Space * Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels) * 10/100 Mb/s Ethernet MAC (EMAC) * IEEE 802.3 Compliant * Media Independent Interface (MII) * 8 Independent Transmit (TX) Channels and 1 Receive (RX) Channel * Management Data Input/Output (MDIO) * Three Configurable Video Ports * Providing a Glueless I/F to Common Video Decoder and Encoder Devices * Supports Multiple Resolutions and Video Standards * VCXO Interpolated Control Port (VIC) * Supports Audio/Video Synchronization * Host-Port Interface (HPI) [32-/16-Bit] * 32-Bit/66-MHz, 3.3-V Peripheral Component Interconnect (PCI) Master/Slave Interface Conforms to PCI Specification 2.2 * Multichannel Audio Serial Port (McASP) * Eight Serial Data Pins * Wide Variety of I2S and Similar Bit Stream Format * Integrated Digital Audio I/F Transmitter Supports S/PDIF, IEC60958-1, AES-3, CP-430 Formats * Inter-Integrated Circuit (I2C) Bus™ * Two Multichannel Buffered Serial Ports * Three 32-Bit General-Purpose Timers * Sixteen General-Purpose I/O (GPIO) Pins * Flexible PLL Clock Generator * IEEE-1149.1 (JTAG) Boundary-Scan-Compatible * 548-Pin Ball Grid Array (BGA) Package (GDK and ZDK Suffixes), 0.8-mm Ball Pitch * 548-Pin Ball Grid Array (BGA) Package (GNZ and ZNZ Suffixes), 1.0-mm Ball Pitch * 0.13-µm/6-Level Cu Metal Process (CMOS) * 3.3-V I/O, 1.2-V Internal (-500) * 3.3-V I/O, 1.4-V Internal (A-500, A-600, -600, -720)

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