TMS320F28034PAGT - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

TMS320F28034PAGT
Manufacturer

TI
ChipWorker Part#

CW8762793
Category

Microcontroller, MCU IC
Package

TQFP-64
Description

MCU 32Bit C28x RISC 128KB Flash 1.8V/3.3V 64Pin TQFP Tray
Documentation

Datasheet

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TMS320F28034PAGT Specifications

Attribute	Attribute Value

Part Number	TMS320F28034PAGT
Manufacturer	TI
ChipWorker Part#	CW8762793
Category	Microcontroller, MCU IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	64 Pin
Case/Package	TQFP-64
Frequency	60 MHz
Number of Positions	64 Position
Clock Speed	60.0 MHz
RAM Memory Size	10 KB
Number of Bits	32 Bit
FLASH Memory Size	128 kB
Number of UARTs	1 UART
Number of ADCs	1 ADC
Number of Inputs and Outputs	33 Input IO
Operating Temperature (Max)	105 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage (Max)	1.995 V
Supply Voltage (Min)	1.71 V
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Size-Height	1.05 mm
Operating Temperature	-40℃ ~ 105℃ (TA)
Product Lifecycle Status	Active
Packaging	Cut Tape (CT)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2014/12/17

Product Description

The TMS320F28034PAGT is a 32-bit Piccolo Microcontroller provides the power of the C28x core and control law accelerator (CLA) coupled with highly integrated control peripherals in low pin-count devices. This family is code-compatible with previous C28x-based code, as well as providing a high level of analog integration. An internal voltage regulator allows for single-rail operation. Enhancements have been made to the HRPWM module to allow for dual-edge control (frequency modulation). Analog comparators with internal 10-bit references have been added and can be routed directly to control the PWM outputs. The ADC converts from 0 to 3.3V fixed full-scale range and supports ratio-metric VREFHI/VREFLO references. The ADC interface has been optimized for low overhead and latency.
High-efficiency 32-bit CPU ( TMS320C28x™)
16 x 16 and 32 x 32 MAC operations
16 x 16 Dual MAC
Harvard bus architecture
Atomic operations
Fast interrupt response and processing
Unified memory programming model
Code-efficient (in C/C++ and assembly)
Endianness - little endian
JTAG boundary scan support
No power sequencing requirement
Integrated power-on and brown-out resets
Two internal zero-pin oscillators
On-chip crystal Oscillator/External clock input
Dynamic PLL ratio changes supported
Watchdog timer module
Missing clock detection circuitry
Peripheral interrupt expansion (PIE) block that supports all peripheral interrupts
Three 32-bit CPU timers
Independent 16-bit timer in each ePWM module

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