TMS320VC33PGE120 - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

TMS320VC33PGE120
Manufacturer

TI
ChipWorker Part#

CW8013033
Category

DSP, Digital Signal Processor
Package

LQFP-144
Description

DSP Floating-Point 32Bit 120MHz 60MIPS 144Pin LQFP
Documentation

Datasheet

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TMS320VC33PGE120 Specifications

Attribute	Attribute Value

Part Number	TMS320VC33PGE120
Manufacturer	TI
ChipWorker Part#	CW8013033
Category	DSP, Digital Signal Processor
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	144 Pin
Case/Package	LQFP-144
Frequency	120 MHz
Supply Voltage (DC)	1.80 V, 3.30 V (max)
RAM Memory Size	136 KB
Number of Bits	32 Bit
Operating Temperature (Max)	90 ℃
Operating Temperature (Min)	0 ℃
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Size-Length	20 mm
Size-Width	20 mm
Size-Height	1.4 mm
Operating Temperature	0℃ ~ 90℃
Product Lifecycle Status	Not Recommended for New Designs
Packaging	Tray
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
ECCN Code	3A991.a.2
HK STC License	NLR

Product Description

description
The TMS320VC33 DSP is a 32-bit, floating-point processor manufactured in 0.18-µm four-level-metal CMOS(TImeline) technology. The TMS320VC33 is part of the TMS320C3x generation of DSPs from Texas
Instruments.
High-Performance Floating-Point Digital Signal Processor (DSP):
− TMS320VC33-150
− 13-ns Instruction Cycle Time
− 150 Million Floating-Point Operations Per Second (MFLOPS)
− 75 Million Instructions Per Second(MIPS)
− TMS320VC33-120
− 17-ns Instruction Cycle Time
− 120 MFLOPS
− 60 MIPS
34K ×32-Bit (1.1-Mbit) On-Chip Words of Dual-Access Static Random-Access Memory (SRAM) Configured in 2 ×16K Plus 2 ×1K Blocks to Improve Internal Performance
x5 Phase-Locked Loop (PLL) Clock Generator
Very Low Power: < 200 mW @ 150 MFLOPS
32-Bit High-Performance CPU
16- /32-Bit Integer and 32- /40-Bit Floating-Point Operations
Four Internally Decoded Page Strobes to Simplify Interface to I/O and Memory Devices
Boot-Program Loader
EDGEMODE Selectable External Interrupts
32-Bit Instruction Word, 24-Bit Addresses
Eight Extended-Precision Registers
On-Chip Memory-Mapped Peripherals:
− One Serial Port
− Two 32-Bit Timers
− Direct Memory Access (DMA) Coprocessor for Concurrent I/O and CPU Operation
Fabricated Using the 0.18-µm (leff-Effective Gate Length) TImelineProcess Technology by Texas Instruments (TI)
144-Pin Low-Profile Quad Flatpack (LQFP) (PGE Suffix)
Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units(ARAUs)
Two Low-Power Modes
Two- and Three-Operand Instructions
Parallel Arithmetic/Logic Unit (ALU) and Multiplier Execution in a Single Cycle
Block-Repeat Capability
Zero-Overhead Loops With Single-Cycle Branches
Conditional Calls and Returns
Interlocked Instructions for Multiprocessing Support
Bus-Control Registers Configure Strobe-Control Wait-State Generation
1.8-V (Core) and 3.3-V (I/O) Supply Voltages
On-Chip Scan-Based Emulation Logic, IEEE Std 1149.1†(JTAG)

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