TMS320VC5410APGE16 - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

TMS320VC5410APGE16
Manufacturer

TI
ChipWorker Part#

CW10740184
Category

DSP, Digital Signal Processor
Package

LQFP-144
Description

DSP Fixed-Point 16Bit 160MHz 160MIPS 144Pin LQFP
Documentation

Datasheet

TMS320VC5410APGE16 Global Supplier

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TMS320VC5410APGE16 Specifications

Attribute	Attribute Value

Part Number	TMS320VC5410APGE16
Manufacturer	TI
ChipWorker Part#	CW10740184
Category	DSP, Digital Signal Processor
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	144 Pin
Case/Package	LQFP-144
Frequency	160 MHz
Supply Voltage (DC)	1.55V (min)
Clock Speed	160 MHz
RAM Memory Size	128 KB
Number of Bits	16 Bit
Operating Temperature (Max)	100 ℃
Operating Temperature (Min)	-40 ℃
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Operating Temperature	-40℃ ~ 100℃
Product Lifecycle Status	Active
Packaging	Tray
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2014/12/17
ECCN Code	3A991.a.2

Product Description

TMS320VC5410A Features
• Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus
• 40-Bit Arithmetic Logic Unit (ALU) Including a 40-Bit Barrel Shifter and Two Independent 40-Bit Accumulators
• 17- × 17-Bit Parallel Multiplier Coupled to a 40-Bit Dedicated Adder for Non-Pipelined Single-Cycle Multiply/Accumulate (MAC) Operation
• Compare, Select, and Store Unit (CSSU) for the Add/Compare Selection of the Viterbi Operator
• Exponent Encoder to Compute an Exponent Value of a 40-Bit Accumulator Value in a Single Cycle
• Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs)
• Data Bus With a Bus Holder Feature
• Extended Addressing Mode for 8M × 16-Bit Maximum Addressable External Program Space
• 64K x 16-Bit On-Chip RAM Composed of Eight Blocks of 8K × 16-Bit On-Chip Dual-Access Program/Data RAM
• 16K × 16-Bit On-Chip ROM Configured for Program Memory
• Enhanced External Parallel Interface (XIO2)
• Single-Instruction-Repeat and Block-Repeat Operations for Program Code
• Block-Memory-Move Instructions for Better Program and Data Management
• Instructions With a 32-Bit Long Word Operand
• Instructions With Two- or Three-Operand Reads
• Arithmetic Instructions With Parallel Store and Parallel Load
• Conditional Store Instructions

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