TPS7350QD - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

TPS7350QD
Manufacturer

TI
ChipWorker Part#

CW8164124
Category

Voltage Regulator
Package

SOIC-8
Description

Single Channel LDO Single Output LDO, 500mA, Fixed(5V), Integrated SVS, Low Quiescent Current LDO Regulator Pos 5V 0.5A 8Pin SOIC Tube
Documentation

Datasheet

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TPS7350QD Specifications

Attribute	Attribute Value

Part Number	TPS7350QD
Manufacturer	TI
ChipWorker Part#	CW8164124
Category	Voltage Regulator
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	8 Pin
Case/Package	SOIC-8
Supply Voltage (DC)	10.0V (max)
Power Rating	0.464 W
Number of Outputs	1 Output
Input Voltage (DC)	10.0V (max)
Output Voltage	5 V
Output Current	500 mA
Number of Positions	8 Position
Power Dissipation	0.725 W
Quiescent Current	0.34 mA
Output Capacitor Type	Ceramic
voltage rating	146 mV
Number of Regulated Outputs	1 Output
Input Voltage (Max)	10 V
Input Voltage (Min)	5.33 V
Output Voltage (Min)	5 V
Output Current (Max)	0.5 A
Operating Temperature (Max)	125 ℃
Operating Temperature (Min)	-40 ℃
Power Dissipation (Max)	725 mW
Accuracy	±2 %
Supply Voltage (Min)	5.33 V
Input Voltage	5.33V ~ 10V
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Size-Length	4.9 mm
Size-Width	3.91 mm
Size-Height	1.58 mm
Operating Temperature	-40℃ ~ 125℃
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2018/06/27
ECCN Code	EAR99

Product Description

The TPS7350QD is a 5V fixed output low-dropout (LDO) Linear Regulator with integrated delay reset function. The RESET\ output of the device initiates a reset in microcomputer and microprocessor systems in the event of an undervoltage condition. An internal comparator in the device monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage. If that occurs, the RESET\ output turns on, taking the RESET\ signal low. RESET\ stays low for the duration of the undervoltage condition. Once the undervoltage condition ceases, a 200ms time-out begins. At the completion of the 200ms delay, RESET\ goes high. An order of magnitude reduction in dropout voltage and quiescent current over conventional LDO performance is achieved by replacing the typical PNP pass transistor with a PMOS device. Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low and is directly proportional to the output current.
Integrated precision supply-voltage supervisor monitoring regulator output voltage
Active-low reset signal with 200ms pulse width
340µA Low quiescent current independent of load
0.5µA Extremely low sleep-state current
2% Tolerance over full range of load, line and temperature
Very low dropout voltage 35mV at IO - 100mA
Green product and no Sb/Br

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