TPS7A9101DSKT - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

TPS7A9101DSKT
Manufacturer

TI
ChipWorker Part#

CW1884800
Category

Voltage Regulator
Package

WFDFN-10
Description

LDO Regulator Pos 0.8V to 5.2V 1A 10Pin WSON EP T/R
Documentation

Datasheet

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TPS7A9101DSKT Specifications

Attribute	Attribute Value

Part Number	TPS7A9101DSKT
Manufacturer	TI
ChipWorker Part#	CW1884800
Category	Voltage Regulator
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	10 Pin
Case/Package	WFDFN-10
Number of Outputs	1 Output
Output Voltage	0.8V ~ 5.2V
Output Current	1.05 A
Number of Positions	10 Position
Quiescent Current	2.10 mA
Output Capacitor Type	Ceramic
voltage rating	200 mV
Number of Regulated Outputs	1 Output
Input Voltage (Max)	6.5 V
Input Voltage (Min)	1.4 V
Output Voltage (Max)	5.2 V
Output Voltage (Min)	800 mV
Output Current (Max)	1 A
Operating Temperature (Max)	125 ℃
Operating Temperature (Min)	-40 ℃
Accuracy	±1 %
Input Voltage	6.5 V
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Operating Temperature	-40℃ ~ 125℃ (TJ)
Product Lifecycle Status	Active
Packaging	Tape & Reel (TR)
RoHS	RoHS Compliant
Lead-Free Status
ECCN Code	EAR99

Product Description

The TPS7A91 is a low-noise (4.7 µVRMS), low-dropout (LDO) voltage regulator capable of sourcing 1 A with only 200 mV of maximum dropout.
The TPS7A91 output is adjustable with external resistors from 0.8 V to 5.2 V. The TPS7A91 wide input-voltage range supports operation as low as 1.4 V and up to 6.5 V.
With 1% output voltage accuracy (over line, load, and temperature) and soft-start capabilities to reduce in-rush current, the TPS7A91 is ideal for powering sensitive analog low-voltage devices [such as voltage-controlled oscillators (VCOs), analog-to-digital converters (ADCs), digital-to-analog converters (DACs), high-end processors, and field-programmable gate arrays (FPGAs)].
The TPS7A91 is designed to power noise-sensitive components such as those found in high-speed communication, video, medical, or test and measurement applications. The very low 4.7-µVRMS output noise and wideband PSRR (40 dB at 1 MHz) minimizes phase noise and clock jitter. These features maximize performance of clocking devices, ADCs, and DACs.

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