TSB12LV26 - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

TSB12LV26
Manufacturer

TI
ChipWorker Part#

CW355902700
RoHS

Lead free / RoHS Compliant
Description

the texas instruments tsb12lv26 device is a pci-to-1394 host controller compliant with the pci local bus specificatio...
Documentation

Datasheet

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TSB12LV26 Specifications

Attribute	Attribute Value

Part Number	TSB12LV26
Manufacturer	TI
ChipWorker Part#	CW355902700
Documentation	Datasheet
Mounting Style	Surface Mount
Case/Package	QFP
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RoHS	RoHS Compliant
Lead-Free Status	Lead Free

Product Description

The Texas Instruments TSB12LV26 device is a PCI-to-1394 host controller compliant with the _PCI Local Bus_ _Specification, PCI Bus Power Management Interface Specification_, IEEE Std 1394-1995, and _1394 Open Host_ _Controller Interface Specification_. The chip provides the IEEE 1394 link function and is compatible with 100M bits/s, 200M bits/s, and 400M bits/s serial bus data rates.
As required by the _1394 Open Host Controller Interface Specification_ (OHCI) and IEEE Std 1394a-2000, internal control registers are memory-mapped and nonprefetchable. The PCI configuration header is accessed through configuration cycles specified by PCI and provides plug-and-play (PnP) compatibility. Furthermore, the TSB12LV26 device is compliant with the _PCI Bus Power Management Interface Specification_, per the _PC 99 Design Guide_ requirements. TSB12LV26 device supports the D0, D2, and D3 power states.
The TSB12LV26 design provides PCI bus master bursting and is capable of transferring a cacheline of data at 132M bytes/s after connection to the memory controller. Since PCI latency can be large, deep FIFOs are provided to buffer 1394 data.
The TSB12LV26 device provides physical write posting buffers and a highly-tuned physical data path for SBP-2 performance. The TSB12LV26 device also provides multiple isochronous contexts, multiple cacheline burst transfers, advanced internal arbitration, and bus-holding buffers on the PHY/link interface.
An advanced CMOS process achieves low power consumption and allows the TSB12LV26 device to operate at PCI clock rates up to 33 MHz.
3.3-V and 5-V PCI bus signaling
3.3-V supply (core voltage is internally regulated to 1.8 V)
Serial bus data rates of 100M bits/s, 200M bits/s, and 400M bits/s
Physical write posting of up to three outstanding transactions
Serial ROM interface supports 2-wire devices
External cycle timer control for customized synchronization
PCI burst transfers and deep FIFOs to tolerate large host latency
Two general-purpose I/Os
Fabricated in advanced low-power CMOS process
Packaged in 100-terminal LQFP (PZT)
PCI_CLKRUN\ protocol
OHCI-Lynx and TI are trademarks of Texas Instruments.

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