TSB81BA3PFP - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

TSB81BA3PFP
Manufacturer

TI
ChipWorker Part#

CW13397640
Category

Interface IC, Interface Controller
Package

HTQFP-80
Description

TEXAS INSTRUMENTS TSB81BA3PFP CABLE TRANSCEIVER/ARBITER, 800Mbps, HTQFP80
Documentation

Datasheet

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TSB81BA3PFP Specifications

Attribute	Attribute Value

Part Number	TSB81BA3PFP
Manufacturer	TI
ChipWorker Part#	CW13397640
Category	Interface IC, Interface Controller
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	80 Pin
Case/Package	HTQFP-80
Supply Voltage (DC)	3.30 V, 3.60 V (max)
Supply Current	120 mA
Number of Positions	80 Position
Data Rate	800 Mbps
Operating Temperature (Max)	70 ℃
Operating Temperature (Min)	0 ℃
Supply Voltage	3V ~ 3.6V
Supply Voltage (Max)	3.6 V
Supply Voltage (Min)	3 V
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Size-Length	12 mm
Size-Width	12 mm
Size-Height	1 mm
Operating Temperature	0℃ ~ 70℃
Product Lifecycle Status	Not Recommended for New Designs
Packaging	Tray
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99
HK STC License	NLR

Product Description

The TSB81BA3PFP is a Digital and Analogue Transceiver functions needed to implement a three-port node in a cable-based IEEE 1394 network. Each cable port incorporates two differential line transceivers. The transceiver includes circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, for packet reception and transmission. It is designed to interface with a link-layer controller (LLC), such as the TSB82AA2, TSB12LV21, TSB12LV26, TSB12LV32, TSB42AA4, TSB42AB4, TSB12LV01B or TSB12LV01C. It may also be connected cable port to cable port to an integrated 1394 Link + PHY layer such as the TSB43AB2. It is powered by dual supplies, a 3.3V supply for I/O and a core voltage supply. The core voltage supply is supplied to the PLLVDD-CORE and DVDD-CORE terminals to the requirements in the recommended operating conditions. It requires an external 98.304MHz crystal oscillator to generate a reference clock.
Fully supports provisions of IEEE P1394b revision 1.33+ at 1-gigabit signalling rates
Fully supports provisions of IEEE 1394a-2000 and 1394-1995 standard for high performance serial bus
Fully interoperable with Fire wire, i.LINK and SB1394™, implementation of IEEE standard 1394
Full 1394a-2000 support includes connection debounce and arbitrated short reset
Power-down features to conserve energy in battery-powered applications
Low-power sleep mode
Fully compliant with open host controller interface (HCI) requirements
Cable power presence monitoring
Cable ports monitor line conditions for active connection to remote node
Interface to link-layer controller supports TI bus-holder isolation
Interoperable with link-layer controllers using 3.3V supplies
Separate bias (TPBIAS) for each port
Software device reset (SWR)
Green product and no Sb/Br

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