TVP5158IPNP - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

TVP5158IPNP
Manufacturer

TI
ChipWorker Part#

CW16392404
Category

CODEC
Package

TQFP-128
Description

Video Decoder 5ADC 10Bit 128Pin HTQFP EP Tray
Documentation

Datasheet

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TVP5158IPNP Specifications

Attribute	Attribute Value

Part Number	TVP5158IPNP
Manufacturer	TI
ChipWorker Part#	CW16392404
Category	CODEC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	128 Pin
Case/Package	TQFP-128
Supply Voltage (DC)	3.00V (min)
Number of Positions	128 Position
Number of Bits	10 Bit
Power Dissipation	643 mW
Number of ADCs	5 ADC
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Power Dissipation (Max)	643 mW
Number of Input Channels	4 Channel
Supply Voltage (Max)	3.6 V
Supply Voltage (Min)	3 V
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Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Not Recommended for New Designs
Packaging	Tray
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The TVP5158IPNP is a 4-channel high-quality NTSC/PAL Video Decoder that digitize and decode all popular base-band analog video formats into digital video output. Each channel of this decoder includes 10bit 27MSPS analog-to-digital converter (ADC). Preceding each ADC in the device, the corresponding analog channel contains an analog circuit that clamps the input to a reference voltage and applies the gain. Composite input signal is sampled at 2x the ITU-R BT.601 clock frequency, line-locked alignment and is then decimated to the 1x pixel rate. CVBS decoding uses five-line adaptive comb filtering for both the luma and chroma data paths to reduce both cross-luma and cross-chroma artifacts. A chroma trap filter is also available. On CVBS inputs, the user can control video characteristics such as contrast, brightness, saturation and hue via an I²C host port interface. TVP5158 provides a glueless audio and video interface to TI DaVinci™ video processors.
Four separate video decoder channels having the following features for each channel
Accepts NTSC (J, M, 4.43) and PAL (B, D, G, H, I, M, N, Nc, 60) video data
Composite video inputs, pseudo-differential video inputs to improved noise immunity
High-speed 10-bit ADC
Fully differential CMOS analog preprocessing channels with clamping
Integrated anti-aliasing filter
2D 5-line (5H) adaptive comb filter
Noise reduction and auto contrast
Robust automatic video standard detection (NTSC/PAL) and switching
Programmable hue, saturation, sharpness, brightness and contrast
Luma-peaking processing
Patented architecture for locking to weak, noisy or unstable signals
Four independent scalers support horizontal and/or vertical 2:1 downscaling
Channel multiplexing capabilities with metadata insertion
Pixel-interleaved mode supports up to four-channel D1 multiplexed 8-bit output at 108MHz
Supports concurrent NTSC and PAL inputs
Support crystal interface with on-chip oscillator and single clock input mode
Single 27MHz Clock input or crystal for all standards and all channels
Internal phase-locked loop (PLL) for line-locked clock (separate for each channel) and sampling
Standard programmable video output format

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