UCC27517ADBVT - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

UCC27517ADBVT
Manufacturer

TI
ChipWorker Part#

CW26157270
Category

FET Driver
Package

SOT-23-5
Description

MOSFET DRVR 4A 1Out Lo Side Inv/Non-Inv 5Pin SOT-23 T/R
Documentation

Datasheet

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UCC27517ADBVT Specifications

Attribute	Attribute Value

Part Number	UCC27517ADBVT
Manufacturer	TI
ChipWorker Part#	CW26157270
Category	FET Driver
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	5 Pin
Case/Package	SOT-23-5
Supply Voltage (DC)	4.50V (min)
Rise/Fall Time	8ns, 7ns
Number of Outputs	1 Output
Number of Positions	5 Position
Rise Time	22 ns
Fall Time	11 ns
Fall Time (Max)	11 ns
Fall Time (Max)	22 ns
Operating Temperature (Max)	140 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	4.5V ~ 18V
Supply Voltage (Max)	18 V
Supply Voltage (Min)	4.5 V
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Operating Temperature	-40℃ ~ 140℃
Product Lifecycle Status	Active
Packaging	Tape & Reel (TR)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
ECCN Code	EAR99

Product Description

The UCC27517ADBVT is a single-channel high-speed low-side Gate Driver with 5V negative input voltage handling ability. It is capable of effectively driving MOSFET and IGBT power switches. Using a design that inherently minimizes shoot-through current, the UCC27517A is capable of sourcing and sinking high peak-current pulses into capacitive loads offering rail-to-rail drive capability and extremely small propagation delay typically 13ns. The device is capable of handling -5V at input. It provides 4A source and 4A sink (symmetrical drive) peak-drive current capability at VDD=12V. It is designed to operate over a wide VDD range of 4.5 to 18V and wide temperature range of -40 to 140°C. Internal under-voltage lockout (UVLO) circuitry on VDD pin holds output low outside VDD operating range.
Gate-driver device offering superior replacement of NPN and PNP discrete solutions
Ability to handle negative voltages (-5V) at inputs
Outputs held low during VDD-UVLO (ensures glitch-free operation at power up and power-down)
TTL and CMOS compatible input-logic threshold (independent of supply voltage)
Hysteretic-logic thresholds for high-noise immunity
Output held low when input pins are floating
Input pin absolute maximum voltage levels not restricted by VDD pin bias supply voltage
9ns and 7ns Typical fast rise and fall time
Green product and no Sb/Br

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