UCC27524AD - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

UCC27524AD
Manufacturer

TI
ChipWorker Part#

CW10590889
Category

FET Driver
Package

SOIC-8
Description

MOSFET DRVR 5A 2Out Lo Side Non-Inv 8Pin SOIC Tube
Documentation

Datasheet

UCC27524AD Global Supplier

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UCC27524AD Specifications

Attribute	Attribute Value

Part Number	UCC27524AD
Manufacturer	TI
ChipWorker Part#	CW10590889
Category	FET Driver
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	8 Pin
Case/Package	SOIC-8
Supply Voltage (DC)	4.50V (min)
Rise/Fall Time	7ns, 6ns
Number of Outputs	2 Output
Number of Positions	8 Position
Rise Time	18 ns
Fall Time	10 ns
Fall Time (Max)	10 ns
Fall Time (Max)	18 ns
Operating Temperature (Max)	140 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	4.5V ~ 18V
Supply Voltage (Max)	18 V
Supply Voltage (Min)	4.5 V
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Operating Temperature	-40℃ ~ 140℃
Product Lifecycle Status	Active
Packaging	Each
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The UCC27524AD is a dual-channel high-speed low-side power MOSFET Driver with negative input voltage ability. It is capable of effectively driving MOSFET and IGBT power switches. The UCC27524A is a variant of the UCC2752x family. The UCC27524A adds the ability to handle -5V directly at the input pins for increased robustness. The UCC27524A is a dual non-inverting driver. Using a design that inherently minimizes shoot-through current, the UCC27524A is capable of delivering high-peak current pulses of up to 5A source and 5A sink into capacitive loads along with rail-to-rail drive capability and extremely small propagation delay typically 13ns. In addition, the driver feature matched internal propagation delays between the two channels which are very well suited for applications requiring dual-gate drive with critical timing, such as synchronous rectifiers.
Industry-standard pin-out
Two independent gate-drive channels
Independent-enable function for each output
TTL and CMOS compatible logic threshold independent of supply voltage
Hysteretic-logic thresholds for high noise immunity
Inputs and enable pin-voltage levels not restricted by VDD pin bias supply voltage
Outputs held low during VDD-UVLO (ensures glitch-free operation at power up and power-down)
Fast propagation delay (13ns typical)
Fast rise and fall time (7 and 6ns typical)
1ns Typical delay matching between 2 channels
Two outputs are paralleled for higher drive current
Outputs held in low when inputs floating
Green product and no Sb/Br

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