UCC27524DGN - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

UCC27524DGN
Manufacturer

TI
ChipWorker Part#

CW40766960
Category

FET Driver
Package

PowerPad-MSOP-8
Description

MOSFET DRVR 5A 2Out Lo Side Non-Inv 8Pin HTSSOP EP Tube
Documentation

Datasheet

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UCC27524DGN Specifications

Attribute	Attribute Value

Part Number	UCC27524DGN
Manufacturer	TI
ChipWorker Part#	CW40766960
Category	FET Driver
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	8 Pin
Case/Package	PowerPad-MSOP-8
Supply Voltage (DC)	4.50V (min)
Rise/Fall Time	7ns, 6ns
Number of Outputs	2 Output
Output Current	5 A
Number of Positions	8 Position
Rise Time	7 ns
Fall Time	7 ns
Fall Time (Max)	10 ns
Fall Time (Max)	18 ns
Operating Temperature (Max)	140 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	4.5V ~ 18V
Supply Voltage (Max)	18 V
Supply Voltage (Min)	4.5 V
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Size-Length	3.1 mm
Size-Width	3.1 mm
Size-Height	0.95 mm
Operating Temperature	-40℃ ~ 140℃
Product Lifecycle Status	Active
Packaging	Each
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The UCC27524DGN is a dual-channel high-speed low-side Gate-driver Device capable of effectively driving MOSFET and IGBT power switches. Using a design that inherently minimizes shoot-through current, UCC2752x can deliver high-peak current pulses of up to 5A source and 5A sink into capacitive loads along with rail-to-rail drive capability and extremely small propagation delay (typically 13ns). In addition, the driver features matched internal propagation delays between the two channels. This delay is very well suited for applications requiring dual-gate drives with critical timing, such as synchronous rectifiers. This also enables connecting two channels in parallel to effectively increase current-drive capability or driving two switches in parallel with one input signal. The input pin thresholds are based on TTL and CMOS compatible low-voltage logic, which is fixed and independent of the VDD supply voltage.
Industry-standard pin-out
Two independent gate-drive channels
Independent-enable function for each output
TTL and CMOS compatible logic threshold independent of supply voltage
Hysteretic-logic thresholds for high noise immunity
Inputs and enable pin-voltage levels not restricted by VDD pin bias supply voltage
Outputs held low during VDD-UVLO (ensures glitch-free operation at power up and power-down)
Two outputs are in parallel for higher drive current
1ns Typical delay matching between two channels
Green product and no Sb/Br

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