UCC27714D - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

UCC27714D
Manufacturer

TI
ChipWorker Part#

CW2925840
Category

FET Driver
Package

SOIC-14
Description

High-Speed, 4A, 600V High-Side Low-Side Gate Driver 14-SOIC -40℃ to 125℃
Documentation

Datasheet

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UCC27714D Specifications

Attribute	Attribute Value

Part Number	UCC27714D
Manufacturer	TI
ChipWorker Part#	CW2925840
Category	FET Driver
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	14 Pin
Case/Package	SOIC-14
Supply Voltage (DC)	10.0V (min)
Rise/Fall Time	15 ns
Number of Outputs	2 Output
Output Current	4 A
Number of Positions	14 Position
Rise Time	15 ns
Fall Time	15 ns
Fall Time (Max)	30 ns
Fall Time (Max)	30 ns
Operating Temperature (Max)	125 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	10V ~ 18V
Supply Voltage (Max)	18 V
Supply Voltage (Min)	10 V
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Operating Temperature	-40℃ ~ 125℃
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The UCC27714D is a high-/low-side Gate Driver with 4A source and 4A sink current capability, targeted to drive power MOSFETs or IGBTs. The device comprises of one ground-referenced channel (LO) and one floating channel (HO) which is designed for operating with bootstrap supplies. The device features excellent robustness and noise immunity with capability to maintain operational logic at negative voltages of up to -8VDC on HS pin (at VDD=12V). The device accepts a wide range bias supply input from 10 to 20V and offers UVLO protection for both the VCC and HB bias supply pins.
High-/low-side configuration with independent inputs
Fully operational up to 600V (HS pin)
Floating channel designed for bootstrap operation
Best-in-class propagation delay (125ns maximum)
Best-in-class delay matching (20ns maximum)
TTL and CMOS compatible input logic
Bias UVLO protection for both channels
Rail-to-rail drive
Robust operation under negative voltage transients
High dv/dt immunity (HS pin)
Separated grounds for logic (VSS) and driver (COM) with capability to sustain voltage difference
Optional enable function (pin 4)
Outputs held in low when inputs floating
Inputs and enable pin-voltage levels not restricted by VDD pin bias supply voltage
High and low voltage pins separated for maximum creepage and clearance
Negative voltage handling capability on input and enable pins
Green product and no Sb/Br

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