XIO1100ZGB - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

XIO1100ZGB
Manufacturer

TI
ChipWorker Part#

CW42526027
Category

Interface IC, Interface Controller
Package

BGA-100
Description

PHY 1CH 1.5V/1.8V/3.3V 100Pin BGA MICROSTAR Tray
Documentation

Datasheet

XIO1100ZGB Global Supplier

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XIO1100ZGB Specifications

Attribute	Attribute Value

Part Number	XIO1100ZGB
Manufacturer	TI
ChipWorker Part#	CW42526027
Category	Interface IC, Interface Controller
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	100 Pin
Case/Package	BGA-100
Supply Voltage (DC)	3.30 V, 1.50 V, 1.80 V
Number of Channels	1 Channel
Operating Temperature (Max)	70 ℃
Operating Temperature (Min)	0 ℃
Supply Voltage (Max)	3.6 V
Supply Voltage (Min)	1.35 V
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Size-Length	12 mm
Size-Width	12 mm
Size-Height	0.9 mm
Product Lifecycle Status	Active
Packaging	Tray
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The XIO1100 is a PCI Express. PHY that is compliant with PCI Express Base Specification Revision 1.1 and that interfaces the PCI Express Media Access Layer (MAC) to a PCI Express serial link by using a modified version of the interface described in PHY Interface for the PCI Express. Architecture (also known as PIPE interface) by Intel Corporation. This modified version of the PIPE interface is referred to as a TI-PIPE interface throughout this data manual.
The TI-PIPE interface is a pin-configurable interface that can be configured as either a 16-bit or an 8-bit interface.
The XIO1100 PHY interfaces to a 2.5 Gbps PCI Express serial link with a transmit differential pair (TXP and TXN) and a receive differential pair (RXP and RXN). Incoming data at the XIO1100 PHY receive differential pair (RXP and RXN) is forwarded to the MAC on the RXDATA output bus. Data received from the MAC on the TXDATA input bus is forwarded to the XIO1100 PHY transfer differential pair (TXP and TXN).
The XIO1100 is also responsible for handling the 8B/10B encoding/decoding and scrambling/unscrambling of the outgoing data. In addition, XIO1100 can recover/interpolate the clock on the receiver side based on the transitions guaranteed by the use of the 8B/10B mechanism and supply this to the receive side of the data link layer logic.
In addition to the TI-PIPE interface, the XIO1100 has some TI-proprietary side-band signals that some customers may wish to use to take advantage of additional XIO1100 low-power state features (for example, disabling the PLL during the L1 power state).

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