ADN2915ACPZ - ADI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

ADN2915ACPZ
Manufacturer

ADI
ChipWorker Part#

CW3780040
Category

Clock Chip, Timing IC
Package

LFCSP-24
Description

CDR 6.5Mbps to 11300Mbps SONET/SDH 24Pin LFCSP EP Tray
Documentation

Datasheet

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ADN2915ACPZ Specifications

Attribute	Attribute Value

Part Number	ADN2915ACPZ
Manufacturer	ADI
ChipWorker Part#	CW3780040
Category	Clock Chip, Timing IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	24 Pin
Case/Package	LFCSP-24
Frequency	176.8 MHz
Supply Voltage (DC)	1.14V (min)
Number of Outputs	1 Output
Supply Current	359.5 mA
Number of Circuits	1 Circuit
Number of Positions	24 Position
Power Dissipation	486.5 mW
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Power Dissipation (Max)	486.5 mW
Supply Voltage	1.14V ~ 3.63V
Supply Voltage (Max)	3.63 V
Supply Voltage (Min)	1.14 V
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Size-Length	4.1 mm
Size-Width	4.1 mm
Size-Height	0.95 mm
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tray
RoHS	RoHS Compliant
Lead-Free Status	Contains Lead
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/12/17
ECCN Code	5A991.b.3

Product Description

The ADN2915ACPZ is a Clock and Data Recovery IC with integrated limiting amplifier/equalizer. The ADN2915 provides the receiver functions of quantization, signal level detect and clock and data recovery for continuous data rates from 6.5Mbps to 11.3Gbps. The ADN2915 automatically locks to all data rates without the need for an external reference clock or programming. ADN2915 jitter performance exceeds all jitter specifications required by SONET/SDH, including jitter transfer, jitter generation and jitter tolerance. The ADN2915 provides manual or automatic slice adjust and manual sample phase adjusts. Additionally, the user can select a limiting amplifier, equalizer or bypass at the input. The equalizer is either adaptive or can be manually set. The receiver front-end loss of signal (LOS) detector circuit indicates when the input signal level has fallen below user-programmable threshold. The LOS detect circuit has hysteresis to prevent chatter at the LOS output.
No reference clock required
Exceeds SONET/SDH requirements for jitter transfer/generation/tolerance
Programmable jitter transfer bandwidth to support G.8251 OTN
Programmable slice level
Programmable LOS threshold via I²C
I²C to access optional features
Loss of lock (LOL) indicator
PRBS Generator/detector

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- Electrical testing
- Surface testing

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