CD74HC107E - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

CD74HC107E
Manufacturer

TI
ChipWorker Part#

CW3594540
Category

Flip Flop IC
Package

DIP-14
Description

Flip Flop JK-Type Neg-Edge 2Element 14Pin PDIP Tube
Documentation

Datasheet

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CD74HC107E Specifications

Attribute	Attribute Value

Part Number	CD74HC107E
Manufacturer	TI
ChipWorker Part#	CW3594540
Category	Flip Flop IC
Documentation	Datasheet
Mounting Style	Through Hole
Number of Pins	14 Pin
Case/Package	DIP-14
Frequency	60 MHz
Supply Voltage (DC)	2.00V (min)
Number of Outputs	1 Output
Output Current	5.2 mA
Number of Circuits	2 Circuit
Number of Channels	2 Channel
Number of Positions	14 Position
Clock Speed	60 MHz
Number of Bits	2 Bit
Input Capacitance	10 pF
Number of Inputs	2 Input
Operating Temperature (Max)	125 ℃
Operating Temperature (Min)	-55 ℃
Supply Voltage	2V ~ 6V
Supply Voltage (Max)	6 V
Supply Voltage (Min)	2 V
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Size-Length	19.3 mm
Size-Width	6.35 mm
Size-Height	4.57 mm
Operating Temperature	-55℃ ~ 125℃
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
ECCN Code	EAR99

Product Description

The CD74HC107E is a high speed CMOS dual negative-edge-triggered J-K Flip-flop with reset. It utilizes silicon gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. It exhibits the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads. This flip-flop has independent J, K, Reset and Clock inputs and Q and Q\ outputs. It changes state on the negative-going transition of the clock pulse. Reset is accomplished asynchronously by a low level input. This device is functionally identical to the HC/HCT73 but differs in terminal assignment and in some parametric limits. The HCT logic family is functionally as well as pin compatible with the standard LS family.
Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times
Asynchronous reset
Complementary outputs
Balanced propagation delay and transition times
Significant power reduction compared to LSTTL logic ICs
High noise immunity
Direct LSTTL input logic compatibility
CMOS Input compatibility
10 LSTTL Load standard outputs
15 LSTTL Load bus driver outputs

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