CD74HC299E - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

CD74HC299E
Manufacturer

TI
ChipWorker Part#

CW11441458
Category

Logic Controller, Logic IC
Package

DIP-20
Description

TEXAS INSTRUMENTS CD74HC299E Shift Register, HC Family, 74HC299, Universal, 1Element, 8Bit, DIP, 20Pins
Documentation

Datasheet

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CD74HC299E Specifications

Attribute	Attribute Value

Part Number	CD74HC299E
Manufacturer	TI
ChipWorker Part#	CW11441458
Category	Logic Controller, Logic IC
Documentation	Datasheet
Mounting Style	Through Hole
Number of Pins	20 Pin
Case/Package	DIP-20
Frequency	50 MHz
Supply Voltage (DC)	5.00 V, 6.00 V (max)
Number of Outputs	10 Output
Number of Circuits	8 Bit Circuit
Number of Positions	20 Position
Number of Bits	8 Bit
Number of Inputs	10 Input
Operating Temperature (Max)	125 ℃
Operating Temperature (Min)	-55 ℃
Supply Voltage	2V ~ 6V
Supply Voltage (Max)	6 V
Supply Voltage (Min)	2 V
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Operating Temperature	-55℃ ~ 125℃
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The CD74HC299E is a 8-bit CMOS universal Shift Register with 3-state outputs. The register has four synchronous-operating modes controlled by the two select inputs as shown in the mode select (S0, S1) table. The mode select, the serial data (DS0, DS7) and the parallel data (I/O0 - I/O7) respond only to the low-to-high transition of the clock (CP) pulse. S0, S1 and data inputs must be one set-up time prior to the clock positive transition. The MR\ is an asynchronous active low input. When MR\ output is low, the register is cleared regardless of the status of all other inputs. The register can be expanded by cascading same units by tying the serial output (Q0) to the serial data (DS7) input of the preceding register and tying the serial output (Q7) to the serial data (DS0) input of the following register. Recirculating the (n x 8) bits is accomplished by tying the Q7 of the last stage to the DS0 of the first stage.
Buffered inputs
Four operating modes - Shift left, shift right, load and store
Can be cascaded for N-bit word lengths
Balanced propagation delay and transition times
Significant power reduction compared to LSTTL logic ICs
High noise immunity
Direct LSTTL input logic compatibility
CMOS Input compatibility
10 LSTTL Loads standard outputs
15 LSTTL Loads bus driver outputs

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