SN65LVDS108DBT - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN65LVDS108DBT
Manufacturer

TI
ChipWorker Part#

CW8779632
Category

LVDS, M-LVDS, ECL, CML IC
Package

TSSOP-38
Description

TEXAS INSTRUMENTS SN65LVDS108DBT LVDS Driver, Differential Buffer / Repeater, 85mA, -40℃, 85℃, 3V
Documentation

Datasheet

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SN65LVDS108DBT Specifications

Attribute	Attribute Value

Part Number	SN65LVDS108DBT
Manufacturer	TI
ChipWorker Part#	CW8779632
Category	LVDS, M-LVDS, ECL, CML IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	38 Pin
Case/Package	TSSOP-38
Supply Voltage (DC)	3.30 V
Number of Outputs	8 Output
Supply Current	85 mA
Number of Positions	38 Position
Power Dissipation	1277 mW
Input Capacitance	5 pF
Input Current (Min)	20 μA
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Power Dissipation (Max)	1277 mW
Supply Voltage	3V ~ 3.6V
Supply Voltage (Max)	3.6 V
Supply Voltage (Min)	3 V
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Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The SN65LVDS108DBT is a 1:8 LVDS Clock Fan-out Buffer. The SN65LVDS108 is configured as one differential line receiver connected to eight differential line drivers. Individual output enables are provided for each output and an additional enable is provided for all outputs. The line receiver and line driver implement the electrical characteristics of low-voltage differential signaling (LVDS). LVDS, as specified in EIA/TIA-644, is a data signaling technique that offers low power, low noise emission, high noise immunity and high switching speeds. The intended application of this device and the LVDS signaling technique, is for point-to-point or point-to-multipoint (distributed simplex) baseband data transmission on controlled impedance media of approximately 100R. The transmission media may be printed-circuit board traces, backplanes or cables.
One line receiver and eight line drivers configured as an 8-port LVDS repeater
Enabling logic allows individual control of each driver output, plus all outputs
Low-voltage differential signalling with typical output voltage of 350mV
Electrically compatible with LVDS, PECL, BTL, SSTL/HSTL outputs with external termination networks
Driver outputs or receiver input equals high impedance when disabled or with VCC <1.5V
400MHz Clock frequency
<4.7ns Propagation delay time
<300ps Output skew
<1.5ns Part-to-part skew
<330mW at 200MHz Typical total power dissipation
Green product and no Sb/Br

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