SN74AUP1T08DCKR - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN74AUP1T08DCKR
Manufacturer

TI
ChipWorker Part#

CW10683400
Category

Logic Control, Logic Gate IC
Package

SC-70-5
Description

Low Power, 1.8/2.5/3.3V Input, 3.3V CMOS Output, 2Input Positive-AND Gate 5-SC70 -40℃ to 85℃
Documentation

Datasheet

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SN74AUP1T08DCKR Specifications

Attribute	Attribute Value

Part Number	SN74AUP1T08DCKR
Manufacturer	TI
ChipWorker Part#	CW10683400
Category	Logic Control, Logic Gate IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	5 Pin
Case/Package	SC-70-5
Supply Voltage (DC)	2.30V (min)
Number of Outputs	1 Output
Number of Circuits	1 Circuit
Number of Positions	5 Position
Number of Bits	1 Bit
Propagation Delay Max (tpd)	10.0 ns
Number of Gates	1 Gate
Number of Inputs	2 Input
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	2.3V ~ 3.6V
Supply Voltage (Max)	3.6 V
Supply Voltage (Min)	2.3 V
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Size-Length	2.15 mm
Size-Width	1.4 mm
Size-Height	1 mm
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tape & Reel (TR)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15

Product Description

DESCRIPTION/ORDERING INFORMATION
The SN74AUP1T08 performs the Boolean function Y = A with designation for logic-level translation applications with output referenced to supply VCC.
AUP technology is the industry"s lowest-power logic technology designed for use in extending battery-life inoperating. All input levels that accept 1.8-V LVCMOS signals, while operating from either a single 3.3-V or 2.5-V VCC supply. This product also maintains excellent signal integrity (see Figure 1 and Figure 2).
FEATURES
• Single-Supply Voltage Translator
• Output Level Up to Supply VCC CMOS Level
– 1.8 V to 3.3 V (at VCC= 3.3 V)
– 2.5 V to 3.3 V (at VCC= 3.3 V)
– 1.8 V to 2.5 V (at VCC= 2.5 V)
– 3.3 V to 2.5 V (at VCC= 2.5 V)
• Schmitt-Trigger Inputs Reject Input Noise and Provide Better Output Signal Integrity
• Ioff Supports Partial Power Down (VCC= 0 V)
• Very Low Static Power Consumption: 0.1 µA
• Very Low Dynamic Power Consumption: 0.9 µA
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• Pb-Free Packages Available: SC-70 (DCK) 2 x 2.1 x 0.65 mm (Height 1.1 mm)
• More Gate Options Available at www.ti.com/littlelogic
• ESD Performance Tested Per JESD 22
– 2000-V Human-Body Model(A114-B, Class II)
– 1000-V Charged-Device Model (C101)

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