SN74LV165APW ,Shift Register IC - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Popularity Score

87 points

Part No

SN74LV165APW
Manufacturer

TI
ChipWorker Part#

CW9426793
Category

Shift Register IC
Package

TSSOP-16
Description

Parallel-Load 8Bit Shift Registers 16-TSSOP -40℃ to 125℃
Documentation

Datasheet
Ships from

Moscow
Наличие

99 pcs In Stock
Estimated Price

$ 0.57

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SN74LV165APW Specifications

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Attribute	Attribute Value

Part Number	SN74LV165APW
Manufacturer	TI
ChipWorker Part#	CW9426793
Category	Shift Register IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	16 Pin
Case/Package	TSSOP-16
Supply Voltage (DC)	2.00V ~ 5.50V
Number of Outputs	1 Output
Number of Circuits	8 Circuit
Number of Positions	16 Position
Number of Bits	8 Bit
Voltage Nodes	5.00 V, 3.30 V, 2.50 V
Static Current	20.0 µA
Output Current Drive	-1.00 mA
Number of Inputs	9 Input
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	2V ~ 5.5V
Supply Voltage (Max)	5.5 V
Supply Voltage (Min)	2 V
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Size-Length	5 mm
Size-Width	4.4 mm
Size-Height	1.15 mm
Operating Temperature	-40℃ ~ 125℃
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
Mil-Spec	Yes
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

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Product Description

The SN74LV165APW is a 8-bit parallel-load Shift Register designed for 2 to 5.5V VCC operation. When it is clocked, data is shifted toward the serial output QH. parallel-in access to each stage is provided by eight individual direct data inputs that are enabled by a low level at the shift/load (SH/LD) input. It features a clock-inhibit function and a complemented serial output, QH. clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD\ is held high and clock inhibit (CLK INH) is held low. The functions of CLK and CLK INH are interchangeable. Since a low CLK and a low-to-high transition of CLK INH accomplishes clocking, CLK INH should be changed to the high level only while CLK is high. parallel loading is inhibited when SH/LD\ is held high. The parallel inputs to the register are enabled while SH/LD\ is held low, independently of the levels of CLK, CLK INH or SER.
Support mixed-mode voltage operation on all ports
Ioff Supports partial-power-down mode operation
Latch-up performance exceeds 250mA per JESD 17
Green product and no Sb/Br

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