SN74LVC2G74DCTR - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN74LVC2G74DCTR
Manufacturer

TI
ChipWorker Part#

CW2483354
Category

Flip Flop IC
Package

SSOP-8
Description

TEXAS INSTRUMENTS SN74LVC2G74DCTR Flip-Flop, Differential / Complementary, Positive Edge, 74LVC74, D, 4.1ns, 200MHz, 32mA, SSOP
Documentation

Datasheet

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SN74LVC2G74DCTR Specifications

Attribute	Attribute Value

Part Number	SN74LVC2G74DCTR
Manufacturer	TI
ChipWorker Part#	CW2483354
Category	Flip Flop IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	8 Pin
Case/Package	SSOP-8
Frequency	200 MHz
Supply Voltage (DC)	5.00 V, 5.50 V (max)
Number of Outputs	1 Output
Output Current	32 mA
Number of Circuits	1 Circuit
Number of Channels	1 Channel
Number of Positions	8 Position
Clock Speed	200 MHz
Number of Bits	1 Bit
Propagation Delay Max (tpd)	4.40 ns
Polarity	Non-Inverting, Inverting
Number of Gates	2 Gate
Input Capacitance	5 pF
Number of Inputs	1 Input
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	1.65V ~ 5.5V
Supply Voltage (Max)	5.5 V
Supply Voltage (Min)	1.65 V
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Size-Length	2.95 mm
Size-Width	2.8 mm
Size-Height	1.2 mm
Operating Temperature	-40℃ ~ 125℃ (TA)
Product Lifecycle Status	Active
Packaging	Tape & Reel (TR)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The SN74LVC2G74DCTR is a single positive-edge-triggered D-type Flip-flop with clear and preset. It is designed for 1.65 to 5.5V VCC operation. A low level at the preset (PRE\\) or clear (CLR\\) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
5.9ns at 3.3V Maximum tpd
Ioff Supports live insertion, partial-power-down mode and back-drive protection
Latch-up performance exceeds 100mA per JESD 78, class II
10µA Maximum low power consumption
±24mA Output drive at 3.3V
Green product and no Sb/Br

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