74HC299D,653 ,Logic Controller, Logic IC - NXP

The pictures are for reference only, and the specific specifications can be found in the product manual.

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76 points

Part No

74HC299D,653
Manufacturer

NXP
ChipWorker Part#

CW57483396
Category

Logic Controller, Logic IC
Package

SOIC-20
Description

NXP 74HC299D,653 Shift Register, HC Family, High-Speed CMOS, 74HC299, Universal, 1Element, 8Bit, SOIC, 20Pins
Documentation

Datasheet
Ships from

Moscow
Наличие

In Stock
Estimated Price

$ 1

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74HC299D,653 Specifications

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Attribute	Attribute Value

Part Number	74HC299D,653
Manufacturer	NXP
ChipWorker Part#	CW57483396
Category	Logic Controller, Logic IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	20 Pin
Case/Package	SOIC-20
Supply Voltage (DC)	2.00V (min)
Number of Outputs	10 Output
Number of Circuits	8 Bit Circuit
Number of Positions	20 Position
Number of Bits	8 Bit
Number of Inputs	10 Input
Operating Temperature (Max)	125 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	2V ~ 6V
Supply Voltage (Max)	6 V
Supply Voltage (Min)	2 V
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Size-Width	7.6 mm
Size-Height	2.45 mm
Operating Temperature	-40℃ ~ 125℃
Product Lifecycle Status	Active
Packaging	Cut Tape (CT)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/12/17

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Product Description

The 74HC299D is a 8-bit Universal Shift Register with 3-state outputs. It contains eight edge-triggered D-type flip-flops and the interstage logic necessary to perform synchronous shift-right, shift-left, parallel load and hold operations. The type of operation is determined by the mode select inputs S0 and S1. Pins I/O0 to I/O7 are flip-flop 3-state buffer outputs which allow them to operate as data inputs in parallel load mode. The serial outputs Q0 and Q7 are used for expansion in serial shifting of longer words. A low signal on the asynchronous master reset input MR\ overrides the Sn and clock CP inputs and resets the flip-flops. All other state changes are initiated by the rising edge of the clock pulse. Inputs can change when the clock is either state, provided that the recommended set-up and hold times are observed. A high signal on the 3-state output enable inputs OE1\ or OE2\ disables the 3-state buffers and the I/on outputs assume a high-impedance OFF-state.
Multiplexed inputs/outputs provide improved bit density
Operates with output enable or at high-impedance OFF-state (Z)
Cascadable for n-bit word lengths
CMOS Input level

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