AD9773 - ADI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

AD9773
Manufacturer

ADI
ChipWorker Part#

CW622300606
Description

12Bit, 160MSPS 2x/4x/8x Interpolating Dual TxDAC+ D/A Converter
Documentation

Datasheet

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Product Description

Product Details
The AD9773 is the 12-bit member of the AD977x pin-compatible, high performance, programmable 2×/4×/8× interpolating TxDAC+® family. The AD977x family features a serial port interface (SPI) that provides a high level of programmability, thus allowing for enhanced system-level options. These options include selectable 2×/4×/8× interpolation filters; fS/2, fS/4, or fS/8 digital quadrature modulation with image rejection; a direct IF mode; programmable channel gain and offset control; programmable internal clock divider; straight binary or twos complement data interface; and a single-port or dual-port data interface.
The selectable 2×/4×/8× interpolation filters simplify the requirements of the reconstruction filters while simultaneously enhancing the TxDAC+ family’s pass-band noise/distortion performance. The independent channel gain and offset adjust registers allow the user to calibrate LO feedthrough and side-band suppression errors associated with analog quadrature modulators. The 6 dB of gain adjustment range can also be used to control the output power level of each DAC.
The AD9773 features the ability to perform fS/2, fS/4, and fS/8 digital modulation and image rejection when combined with an analog quadrature modulator. In this mode, the AD9773 accepts I and Q complex data (representing a single or multi-carrier waveform), generates a quadrature modulated IF signal along with its orthogonal representation via its dual DACs, and presents these two reconstructed orthogonal IF carriers to an analog quadrature modulator to complete the image rejection upconversion process. Another digital modulation mode (for example, the direct IF mode) allows the original baseband signal representation to be frequency translated such that pairs of images fall at multiples of one-half the DAC update rate.
Dual high performance DAC outputs provide a differential current output programmable over a 2 mA to 20 mA range. The AD9773 is manufactured on an advanced 0.35 micron CMOS process, operates from a single supply of 3.1 V to 3.5 V, and consumes 1.2 W of power.
**Product Highlights**
1. The AD9773 is the 12-bit member of the AD977x pin compatible, high performance, programmable 2×/4×/8× interpolating TxDAC+ family.
2. Direct IF transmission is possible for 70 MHz + IFs through a novel digital mixing process.
3. fS/2, fS/4, and fS/8 digital quadrature modulation and user selectable image rejection simplify/remove cascaded SAW filter stages.
4. A 2×/4×/8× user selectable interpolating filter eases data rate and output signal reconstruction filter requirements.
5. User selectable twos complement/straight binary data coding.
6. User programmable channel gain control over 1 dB range in 0.01 dB increments.
7. User programmable channel offset control ±10% over the FSR.
8. Ultrahigh speed 400 MSPS DAC conversion rate.
9. Internal clock divider provides data rate clock for easy interfacing.
10. Flexible clock input with single-ended or differential input, CMOS, or 1 V p-p LO sine wave input capability.
11. Low power: Complete CMOS DAC operates on 1.2 W from a 3.1 V to 3.5 V single supply. The 20 mA full-scale current can be reduced for lower power operation, and several sleep functions reduce power during idle periods.
12. On-chip voltage reference: The AD9773 includes a 1.20 V temperature compensated band gap voltage reference.
13. 80-lead thin quad flat package, exposed pad (TQFP_EP).
### Features and Benefits
12-bit resolution, 160 MSPS/400 MSPS input/output data rate
Selectable 2×/4×/8× interpolating filter
Programmable channel gain and offset adjustment
fS/2, fS/4, fS/8 digital quadrature modulation capability
Direct IF transmission mode for 70 MHz + IFs
Excellent ac performance
SFDR −69 dBc @ 2 MHz to 35 MHz
WCDMA ACPR −69 dB @ IF = 19.2 MHz
Enables image rejection architecture
Fully compatible SPI port
Internal PLL clock multiplier
Selectable internal clock divider
Versatile clock input
Differential/single-ended sine wave or TTL/CMOS/LVPECL compatible
Versatile input data interface
Twos complement/straight binary data coding
Dual-port or single-port interleaved input data

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