CD4015BE - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

CD4015BE
Manufacturer

TI
ChipWorker Part#

CW1262404
Category

Shift Register IC
Package

DIP-16
Description

TEXAS INSTRUMENTS CD4015BE Shift Register, CD4015, Serial to Parallel, 2Element, 4Bit, DIP, 16Pins
Documentation

Datasheet

CD4015BE Global Supplier

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CD4015BE Specifications

Attribute	Attribute Value

Part Number	CD4015BE
Manufacturer	TI
ChipWorker Part#	CW1262404
Category	Shift Register IC
Documentation	Datasheet
Mounting Style	Through Hole
Number of Pins	16 Pin
Case/Package	DIP-16
Frequency	17 MHz
Supply Voltage (DC)	15.0 V, 18.0 V (max)
Operating Voltage	3V ~ 18V
Number of Outputs	4 Output
Supply Current	600 μA
Number of Circuits	2 Circuit
Number of Positions	16 Position
Number of Bits	4 Bit
Voltage Nodes	5.00 V, 10.0 V, 15.0 V
Power Dissipation	500 mW
Input Capacitance	5 pF
Number of Inputs	1 Input
Operating Temperature (Max)	125 ℃
Operating Temperature (Min)	-55 ℃
Supply Voltage	3V ~ 18V
Supply Voltage (Max)	18 V
Supply Voltage (Min)	3 V
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Size-Width	6.35 mm
Operating Temperature	-55℃ ~ 125℃
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The CD4015BE is a 4-stage CMOS dual static Shift Register consists of two identical, independent, 4-stage serial-input/parallel-output registers. Each register has independent clock and RESET inputs as well as a single serial DATA input. "Q" outputs are available from each of the four stages on both registers. All register stages are D-type, master-slave flip-flops. The logic level present at the DATA input is transferred into the first register stage and shifted over one stage at each positive-going clock transition. Resetting of all stages is accomplished by a high level on the RESET line.
Fully static operation
Standardized, symmetrical output characteristics
Meets all requirements of JEDEC tentative standard no. 13B
8 Master-slave flip-flops plus input and output buffering
100% Tested for quiescent current at 20V
Green product and no Sb/Br

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