CD4018BE ,Logic Controller, Logic IC - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Popularity Score

180 points

Part No

CD4018BE
Manufacturer

TI
ChipWorker Part#

CW1529483
Category

Logic Controller, Logic IC
Package

PDIP-16
Description

TEXAS INSTRUMENTS CD4018BE Divide-By-N Counter Counter, 8.5MHz, 3V to 18V, DIP-16
Documentation

Datasheet
Ships from

Moscow
Наличие

In Stock
Estimated Price

$ 0.43

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CD4018BE Specifications

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Attribute	Attribute Value

Part Number	CD4018BE
Manufacturer	TI
ChipWorker Part#	CW1529483
Category	Logic Controller, Logic IC
Documentation	Datasheet
Mounting Style	Through Hole
Number of Pins	16 Pin
Case/Package	PDIP-16
Digital Logic Level	CMOS
Supply Voltage (DC)	3.00V ~ 18.0V
Number of Outputs	5 Output
Output Current	6.80 mA
Number of Positions	16 Position
Clock Speed	8.5 MHz
Number of Bits	5 Bit
Voltage Nodes	5.00 V, 10.0 V, 15.0 V
Power Dissipation	100 mW
Number of Inputs	1 Input
Operating Temperature (Max)	125 ℃
Operating Temperature (Min)	-55 ℃
Supply Voltage	3V ~ 18V
Supply Voltage (Max)	18 V
Supply Voltage (Min)	3 V
	expand all
Operating Temperature	-55℃ ~ 125℃
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99
HK STC License	NLR

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Product Description

The CD4018BE is a CMOS Pre-settable divide-by-N Counter consists of 5 Johnson-counter stages, buffered Q outputs from each stage and counter pre-set control gating. CLOCK, RESET, DATA, PRESET ENABLE and 5 individual JAM inputs are provided. Divide by 10, 8, 6, 4 or 2 counter configurations can be implemented by feeding the Q\5, Q\4, Q\3, Q\2, Q\1 signals respectively, back to the DATA input. Divide-by functions greater than 10 can be achieved by use of multiple CD4018B units. The counter is advanced one count at the positive clock-signal transition. Schmitt Trigger action on the clock line permits unlimited clock rise and fall times. A high RESET signal clears the counter to an all-zero condition. A high PRESET-ENABLE signal allows information on the JAM inputs to pre-set the counter. Anti-lock gating is provided to assure the proper counting sequence.
Fully static operation
100% Tested for quiescent current at 20V
Standardized, symmetrical output characteristics
Meets all requirements of JEDEC tentative standard #13B

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