CD74HC190E - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

CD74HC190E
Manufacturer

TI
ChipWorker Part#

CW16797940
Category

Logic Controller, Logic IC
Package

PDIP-16
Description

TEXAS INSTRUMENTS CD74HC190E BCD Decade Up / Down Counter, HC Family, 35MHz, 2V to 6V, DIP-16
Documentation

Datasheet

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CD74HC190E Specifications

Attribute	Attribute Value

Part Number	CD74HC190E
Manufacturer	TI
ChipWorker Part#	CW16797940
Category	Logic Controller, Logic IC
Documentation	Datasheet
Mounting Style	Through Hole
Number of Pins	16 Pin
Case/Package	PDIP-16
Supply Voltage (DC)	2.00V (min)
Number of Outputs	4 Output
Number of Positions	16 Position
Clock Speed	35 MHz
Number of Bits	4 Bit
Number of Inputs	4 Input
Operating Temperature (Max)	125 ℃
Operating Temperature (Min)	-55 ℃
Supply Voltage	2V ~ 6V
Supply Voltage (Max)	6 V
Supply Voltage (Min)	2 V
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Size-Length	19.3 mm
Size-Width	6.35 mm
Size-Height	4.57 mm
Operating Temperature	-55℃ ~ 125℃
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The CD74HC190E is a high speed CMOS presettable synchronous BCD decade Up/Down Counter presets the counter to the number on preset data inputs (A-D) is accomplished by a low asynchronous parallel load (LOAD\\) input. Counting occurs when LOAD\ is high, count enable (CTEN\\) is low and the down/up (D/U) input is either high for down counting or low for up counting. The counter is decremented or incremented synchronously with the low-to-high transition of the clock. When an overflow or underflow of the counter occurs, the MAX/MIN output, which is low during counting, goes high and remains high for one clock cycle. This output can be used for look-ahead carry in high-speed cascading. The MAX/MIN output also initiates the ripple clock (RCO\\) output, which is normally high, goes low and remains low for the low-level portion of the clock pulse.
Synchronous counting and asynchronous loading
Two outputs for n-bit cascading
Look-ahead carry for high-speed counting
Balanced propagation delay and transition times
Standard outputs drive up to 15 LS-TTL loads
Significant power reduction compared to LS-TTL logic ICs

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