CD74HC573M96 - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

CD74HC573M96
Manufacturer

TI
ChipWorker Part#

CW7523729
Category

Latche IC
Package

SOIC-20
Description

Latch Transparent 3-ST 8CH D-Type 20Pin SOIC T/R
Documentation

Datasheet

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CD74HC573M96 Specifications

Attribute	Attribute Value

Part Number	CD74HC573M96
Manufacturer	TI
ChipWorker Part#	CW7523729
Category	Latche IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	20 Pin
Case/Package	SOIC-20
Supply Voltage (DC)	5.00 V, 6.00 V (max)
Number of Outputs	8 Output
Output Current	7.8 mA
Number of Circuits	8 Circuit
Number of Positions	20 Position
Number of Bits	8 Bit
Polarity	Non-Inverting
Number of Inputs	8 Input
Operating Temperature (Max)	125 ℃
Operating Temperature (Min)	-55 ℃
Supply Voltage	2V ~ 6V
Supply Voltage (Max)	6 V
Supply Voltage (Min)	2 V
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Size-Length	12.8 mm
Size-Width	7.52 mm
Size-Height	2.35 mm
Operating Temperature	-55℃ ~ 125℃
Product Lifecycle Status	Active
Packaging	Cut Tape (CT)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The CD74HC573M96 is an octal CMOS Transparent D Latch with 3-state outputs. This high speed latch is designed for 2 to 6V VCC operation. When the LE input is high, the Q outputs follow the data (D) inputs. When LE is low, the Q outputs are latched at the logic levels of the D inputs. A buffered OE\ input can be used to place the eight outputs in either a normal logic state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pull-up components. OE\ does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pull-up resistor.
Balanced propagation delays and transition times
Bus driver outputs drive up to 15 LS-TTL loads
Significant power reduction compared to LS-TTL logic ICs
Green product and no Sb/Br

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