CD74HC7046AE - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

CD74HC7046AE
Manufacturer

TI
ChipWorker Part#

CW11502134
Category

Phase Locked Loop, PLL IC
Package

PDIP-16
Description

PLL Single 12MHz to 18MHz 16Pin PDIP Tube
Documentation

Datasheet

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CD74HC7046AE Specifications

Attribute	Attribute Value

Part Number	CD74HC7046AE
Manufacturer	TI
ChipWorker Part#	CW11502134
Category	Phase Locked Loop, PLL IC
Documentation	Datasheet
Mounting Style	Through Hole
Number of Pins	16 Pin
Case/Package	PDIP-16
Frequency	38 MHz
Supply Voltage (DC)	2.00V (min)
Supply Current	8.00 µA
Number of Circuits	1 Circuit
Number of Positions	16 Position
Number of Bits	1 Bit
Voltage Nodes	6.00 V, 5.00 V, 2.00 V
Operating Temperature (Max)	125 ℃
Operating Temperature (Min)	-55 ℃
Supply Voltage	2V ~ 6V
Supply Voltage (Max)	6 V
Supply Voltage (Min)	2 V
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Size-Length	19.69 mm
Size-Width	6.6 mm
Size-Height	4.57 mm
Operating Temperature	-55℃ ~ 125℃
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

Description
The CD74HC7046A and CD74HCT7046A high-speed silicon-gate CMOS devices, specified in compliance with JEDEC Standard No. 7A, are phase-locked-loop (PLL) circuits that contain a linear voltage-controlled oscillator (VCO), two-phase comparators (PC1, PC2), and a lock detector. A signal input and a comparator input are common to each comparator. The lock detector gives a HIGH level at pin 1 (LD) when the PLL is locked. The lock detector capacitor must be connected between pin 15 (CLD) and pin 8 (Gnd). For a frequency range of 100kHz to 10MHz, the lock detector capacitor should be 1000pF to 10pF, respectively.
Features
• Center Frequency of 18MHz (Typ) at VCC = 5V, Minimum Center Frequency of 12MHz at VCC = 4.5V
• Choice of Two Phase Comparators
- Exclusive-OR
- Edge-Triggered JK Flip-Flop
• Excellent VCO Frequency Linearity
• VCO-Inhibit Control for ON/OFF Keying and for Low Standby Power Consumption
• Minimal Frequency Drift
• Zero Voltage Offset Due to Op-Amp Buffer
• Operating Power-Supply Voltage Range
- VCO Section . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 6V
- Digital Section . . . . . . . . . . . . . . . . . . . . . . . . 2V to 6V
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
Applications
• FM Modulation and Demodulation
• Frequency Synthesis and Multiplication
• Frequency Discrimination
• Tone Decoding
• Data Synchronization and Conditioning
• Voltage-to-Frequency Conversion
• Motor-Speed Control
• Related Literature
- AN8823, CMOS Phase-Locked-Loop Application Using the CD74HC/HCT7046A and CD74HC/HCT7046A

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