CDCLVD2102RGTT - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

CDCLVD2102RGTT
Manufacturer

TI
ChipWorker Part#

CW2439993
Category

Clock Buffer, Driver, PLL IC
Package

QFN-16
Description

Clock Fanout Buffer 8Out 2IN Dual 1:2 16Pin VQFN EP T/R
Documentation

Datasheet

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CDCLVD2102RGTT Specifications

Attribute	Attribute Value

Part Number	CDCLVD2102RGTT
Manufacturer	TI
ChipWorker Part#	CW2439993
Category	Clock Buffer, Driver, PLL IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	16 Pin
Case/Package	QFN-16
Frequency	800 MHz
Supply Voltage (DC)	2.50 V
Number of Outputs	2 Output
Supply Current	76.0 mA
Number of Circuits	2 Circuit
Number of Positions	16 Position
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	2.375V ~ 2.625V
Supply Voltage (Max)	2.625 V
Supply Voltage (Min)	2.375 V
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Size-Length	3.15 mm
Size-Width	3.15 mm
Size-Height	0.95 mm
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tape & Reel (TR)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The CDCLVD2102RGTT is a Clock Buffer distributes two clock inputs (IN0, IN1) to a total of 4 pairs of differential LVDS clock outputs (OUT0, OUT3). Each buffer block consists of one input and 2 LVDS outputs. The inputs can either be LVDS, LVPECL or LVCMOS. It is specifically designed for driving 50R transmission lines. If driving the inputs in single ended mode, the appropriate bias voltage (VAC_REF) should be applied to the unused negative input pin. Using the control pin (EN), outputs can be either disabled or enabled. If the EN pin is left open two buffers with all outputs are enabled, if switched to a logical 0 both buffers with all outputs are disabled (static logical 0), if switched to a logical 1, one buffer with two outputs is disabled and another buffer with two outputs is enabled. The part supports a fail-safe function. It incorporates an input hysteresis, which prevents random oscillation of the outputs in absence of an input signal.
1:2 Differential buffer
Universal inputs accept LVDS, LVPECL and LVCMOS
One input dedicated for two outputs
4 LVDS outputs, ANSI EAI/TIA-644A standard compatible
<300fs RMS in 10kHz to 20MHz low additive jitter
15ps Maximum low output skew
Green product and no Sb/Br
Device has limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

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