CDCM61002RHBT - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

CDCM61002RHBT
Manufacturer

TI
ChipWorker Part#

CW2566044
Category

Clock Generator IC
Package

VQFN-32
Description

Clock Generator 21.875MHz to 28.47MHz Input 683.264MHz Output 32Pin VQFN EP T/R
Documentation

Datasheet

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CDCM61002RHBT Specifications

Attribute	Attribute Value

Part Number	CDCM61002RHBT
Manufacturer	TI
ChipWorker Part#	CW2566044
Category	Clock Generator IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	32 Pin
Case/Package	VQFN-32
Frequency	683.28 MHz
Supply Voltage (DC)	3.30 V
Number of Outputs	2 Output
Supply Current	120 mA
Number of Circuits	1 Circuit
Number of Positions	32 Position
Input Current	200 mA
Duty Cycle	55% (Max)
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	3V ~ 3.6V
Supply Voltage (Max)	3.6 V
Supply Voltage (Min)	3 V
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Size-Length	5.15 mm
Size-Width	5.15 mm
Size-Height	0.95 mm
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tape & Reel (TR)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The CDCM61002RHBT is a highly versatile Frequency Synthesizer can generate two low-jitter clock outputs, selectable between low-voltage positive emitter coupled logic (LVPECL), low-voltage differential signalling (LVDS) or low-voltage complementary metal oxide semiconductor (LVCMOS) outputs, from a low-frequency crystal or LVCMOS input for a variety of wire line and data communication applications. The CDCM61002 features an onboard PLL that can be easily configured solely through control pins. The overall output random jitter performance is less than 1ps, RMS. It is a high-performance, low phase noise, fully-integrated voltage-controlled oscillator (VCO) clock synthesizer with two universal output buffers that can be configured to be LVPECL, LVDS or LVCMOS compatible. Each universal output can also be converted to two LVCMOS outputs.
One Crystal/LVCMOS reference input
LVCMOS Bypass output
Supports common LVPECL/LVDS output frequencies
Supports common LVCMOS output frequencies
High-performance PLL core
Output duty cycle corrected to 50% (±5%)
Divider programming using control pins
Chip enable control pin
ESD Protection exceeds 2kV (HBM)
400kHz Internal PLL loop bandwidth
Green product and no Sb/Br

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