DS90C363BMT - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

DS90C363BMT
Manufacturer

TI
ChipWorker Part#

CW41021526
Category

Interface IC, Interface Controller
Package

TSSOP-48
Description

+3.3V Programmable LVDS Transmitter 18Bit Flat Panel Display (FPD) Link - 65MHz 48-TSSOP -10 to 70
Documentation

Datasheet

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DS90C363BMT Specifications

Attribute	Attribute Value

Part Number	DS90C363BMT
Manufacturer	TI
ChipWorker Part#	CW41021526
Category	Interface IC, Interface Controller
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	48 Pin
Case/Package	TSSOP-48
Supply Voltage (DC)	3.00V (min)
Number of Positions	48 Position
Power Dissipation	1980 W
Data Rate	455 Mbps
Input Current (Min)	10 μA
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Power Dissipation (Max)	1980 mW
Supply Voltage	3V ~ 3.6V
Supply Voltage (Max)	3.6 V
Supply Voltage (Min)	3 V
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Product Lifecycle Status	Active
Packaging	Tube
RoHS	Non-Compliant
Lead-Free Status	Contains Lead
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The DS90C363BMT is a 3.3V programmable LVDS Transmitter converts 21-bits of CMOS/TTL data into three LVDS (low voltage differential signalling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21-bits of input data are sampled and transmitted. At a transmit clock frequency of 65MHz, 18-bits of RGB data and 3-bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455Mbps per LVDS data channel. Using a 65MHz clock, the data throughput is 170Mbps. The DS90C363B transmitter can be programmed for rising edge strobe or falling edge strobe through a dedicated pin. A rising edge or falling edge strobe transmitter will interoperate with a Falling edge strobe receiver (DS90CF366) without any translation logic. This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces.
No special start-up sequence required between clock/data and /PD pins
Input signal (clock and data) can be applied either before or after the device is powered
Supports spread spectrum clocking up to 100kHz frequency modulation
Supports deviation of ±2.5% centre spread or -5% down spread
Best-in-class set and hold times on TxINPUTs
40% Less power dissipation than BiCMOS alternatives
Narrow bus reduces cable size
Up to 1.3Gbps throughput
Up to 170Mbps bandwidth
345mV Typical Swing LVDS devices for low EMI
PLL requires no external components
Compatible with TIA/EIA-644 LVDS standard
Device has limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

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