MC100EPT21MNR4G ,Voltage Level Translator IC - ON Semiconductor
The pictures are for reference only, and the specific specifications can be found in the product manual.
Popularity Score
115 points
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Part NoMC100EPT21MNR4G
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ManufacturerON Semiconductor
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ChipWorker Part#CW11397334
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CategoryVoltage Level Translator IC
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PackageDFN-8
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DescriptionTranslator CML/LVDS/LVPECL to LVCMOS/LVTTL 8Pin DFN EP T/R
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DocumentationDatasheet
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Ships fromMoscow
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Наличие102814 pcs In Stock
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Estimated Price$ 1.7
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MC100EPT21MNR4G Specifications
Consulting Engineer >>| Attribute | Attribute Value | |
|---|---|---|
| Part Number | MC100EPT21MNR4G | |
| Manufacturer | ON Semiconductor | |
| ChipWorker Part# | CW11397334 | |
| Category | Voltage Level Translator IC | |
| Documentation | Datasheet | |
| Mounting Style | Surface Mount | |
| Number of Pins | 8 Pin | |
| Case/Package | DFN-8 | |
| Halogen Free Status | Halogen Free | |
| Number of Circuits | 1 Circuit | |
| Number of Channels | 1 Channel | |
| Number of Positions | 8 Position | |
| Number of Bits | 1 Bit | |
| Number of Inputs | 2 Input | |
| Operating Temperature (Max) | 85 ℃ | |
| Operating Temperature (Min) | -40 ℃ | |
| Number of Output Channels | 1 Channel | |
| Supply Voltage | 3V ~ 3.6V | |
| Supply Voltage (Max) | 3.6 V | |
| Supply Voltage (Min) | 3 V | |
| expand all | ||
| Operating Temperature | -40℃ ~ 85℃ (TA) | |
| Product Lifecycle Status | Active | |
| Packaging | Tape & Reel (TR) | |
| RoHS | RoHS Compliant | |
| Lead-Free Status | Lead Free | |
| ECCN Code | EAR99 |
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Product Description
- The MC100EPT21 is a Differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL (Positive ECL), LVDS, and positive CML input levels and LVTTL/LVCMOS output levels are used, only +3.3 V and ground are required. The small outline 8−lead SOIC package makes the EPT21 ideal for applications which require the translation of a clock or data signal.
- The VBB output allows this EPT21 to be cap coupled in either single−ended or differential input mode. When single−ended cap coupled, VBB output is tied to the D input and D is driven for a non−inverting buffer, or VBB output is tied to the D input and D is driven for an inverting buffer. When cap coupled differentially, VBB output is connected through a resistor to each input pin. If used, the VBB pin should be bypassed to VCC via a 0.01 μF capacitor. For additional information see AND8020/D. For a single−ended direct connection use an external voltage reference source such as a resistor divider. Do not use VBB for a single−ended direct connection or port to another device.
- Features
- • 1.4 ns Typical Propagation Delay
- • Maximum Frequency > 275 MHz Typical
- • LVPECL/LVDS/CML Inputs, LVTTL/LVCMOS Outputs
- • 24 mA TTL outputs
- • Operating Range: VCC = 3.0 V to 3.6 V with GND = 0 V
- • The 100 Series Contains Temperature Compensation
- • VBB Output
- • Pb−Free Packages are Available
Delivery
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