S4MF06607BSPZQQ1 - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

S4MF06607BSPZQQ1
Manufacturer

TI
ChipWorker Part#

CW27589128
Category

Microcontroller, MCU IC
Package

LQFP-100
Description

MCU 16Bit/32Bit TMS470M ARM Cortex M3 RISC 640KB Flash 1.55V/3.3V 100Pin LQFP Tray
Documentation

Datasheet

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S4MF06607BSPZQQ1 Specifications

Attribute	Attribute Value

Part Number	S4MF06607BSPZQQ1
Manufacturer	TI
ChipWorker Part#	CW27589128
Category	Microcontroller, MCU IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	100 Pin
Case/Package	LQFP-100
Frequency	80 MHz
Clock Speed	80.0 MHz
RAM Memory Size	64 KB
FLASH Memory Size	655360 B
Number of ADCs	1 ADC
Operating Temperature (Max)	125 ℃
Operating Temperature (Min)	-40 ℃
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Operating Temperature	-40℃ ~ 125℃ (TA)
Product Lifecycle Status	Active
Packaging	Tray
RoHS	RoHS Compliant
Lead-Free Status	Lead Free

Product Description

The TMS470MF06607 device is a member of the Texas Instruments TMS470M family of Automotive Grade 16/32-bit reduced instruction set computer (RISC) microcontrollers. The TMS470M microcontrollers offer high performance utilizing the high efficiency ARM Cortex™-M3 16/32-bit RISC central processing unit (CPU), resulting in a high instruction throughput while maintaining greater code efficiency.
High-end embedded control applications demand more performance from their controllers while maintaining low costs. The TMS470M microcontroller architecture offers solutions to these performance and cost demands while maintaining low power consumption.
The TMS470MF06607 device contains the following:
The TMS470M memory includes general-purpose SRAM supporting single-cycle read/write accesses in byte, half-word, and word modes. The SRAM on the TMS470M devices can be protected by means of ECC. This feature utilizes a single error correction and double error detection circuit (SECDED circuit) to detect and optionally correct single bit errors as well as detect all dual bit and some multi-bit errors. This is achieved by maintaining an 8-bit ECC checksum/code for each 64-bit double-word of memory space in a separate ECC RAM memory space.

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