SM320F2812PGFMEP - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SM320F2812PGFMEP
Manufacturer

TI
ChipWorker Part#

CW56276529
Category

DSP, Digital Signal Processor
Package

LQFP-176
Description

DSP Fixed-Point 32Bit 150MHz 150MIPS 176Pin LQFP
Documentation

Datasheet

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SM320F2812PGFMEP Specifications

Attribute	Attribute Value

Part Number	SM320F2812PGFMEP
Manufacturer	TI
ChipWorker Part#	CW56276529
Category	DSP, Digital Signal Processor
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	176 Pin
Case/Package	LQFP-176
Frequency	150 MHz
Clock Speed	150 MHz
RAM Memory Size	36 KB
FLASH Memory Size	256 KB
Number of UARTs	2 UART
Number of ADCs	1 ADC
Operating Temperature (Max)	125 ℃
Operating Temperature (Min)	-55 ℃
	expand all
Product Lifecycle Status	Active
Packaging	Tray
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	3A001.a.2.c

Product Description

* Controlled Baseline * One Assembly/Test/Fabrication Site * Extended Temperature Performance of –55°C to 125°C * Enhanced Diminishing Manufacturing Sources (DMS) Support * Enhanced Product-Change Notification * Qualification Pedigree(1) * High-Performance Static CMOS Technology * 150 MHz (6.67-ns Cycle Time) * Low-Power (1.8-V Core @135 MHz, 1.9-V Core @150 MHz, 3.3-V I/O) Design * JTAG Boundary Scan Support(2) * High-Performance 32-Bit CPU (320C28x) * 16 × 16 and 32 × 32 MAC Operations * 16 × 16 Dual MAC * Harvard Bus Architecture * Atomic Operations * Fast Interrupt Response and Processing * Unified Memory Programming Model * 4M Linear Program/Data Address Reach * Code-Efficient (in C/C++ and Assembly) * 320F24x/LF240x Processor Source Code Compatible * On-Chip Memory * Flash Devices: Up to 128K × 16 Flash (Four 8K × 16 and Six 16K × 16 Sectors) * ROM Devices: Up to 128K × 16 ROM * 1K × 16 OTP ROM * L0 and L1: 2 Blocks of 4K × 16 Each Single-Access RAM (SARAM) * H0: 1 Block of 8K × 16 SARAM * M0 and M1: 2 Blocks of 1K × 16 Each SARAM * Boot ROM (4K × 16) * With Software Boot Modes * Standard Math Tables * External Interface (2812) * Over 1M × 16 Total Memory * Programmable Wait States * Programmable Read/Write Strobe Timing * Three Individual Chip Selects * Clock and System Control * Dynamic PLL Ratio Changes Supported * On-Chip Oscillator * Watchdog Timer Module * Three External Interrupts * Peripheral Interrupt Expansion (PIE) Block That Supports 45 Peripheral Interrupts * Three 32-Bit CPU-Timers * 128-Bit Security Key/Lock * Protects Flash/ROM/OTP and L0/L1 SARAM * Prevents Firmware Reverse Engineering * Motor Control Peripherals * Two Event Managers (EVA, EVB) * Compatible to 240xA Devices * Serial Port Peripherals * Serial Peripheral Interface (SPI) * Two Serial Communications Interfaces (SCIs), Standard UART * Enhanced Controller Area Network (eCAN) * Multichannel Buffered Serial Port (McBSP) * 12-Bit ADC, 16 Channels * 2 × 8 Channel Input Multiplexer * Two Sample-and-Hold * Single/Simultaneous Conversions * Fast Conversion Rate: 80 ns/12.5 MSPS * Up to 56 General Purpose I/O (GPIO) Pins * Advanced Emulation Features * Analysis and Breakpoint Functions * Real-Time Debug via Hardware * Development Tools Include * ANSI C/C++ Compiler/Assembler/Linker * Code Composer Studio™ IDE * DSP/BIOS™ * Low-Power Modes and Power Savings * IDLE, STANDBY, HALT Modes Supported * Disable Individual Peripheral Clocks * Package Options * 179-Ball MicroStar BGA™ (GHH), (2812) * 176-Pin Low-Profile Quad Flatpack (LQFP) (PGF) (2812)

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