SN65LVCP114ZJA - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN65LVCP114ZJA
Manufacturer

TI
ChipWorker Part#

CW18852393
Category

Interface IC, Interface Controller
Package

NFBGA-167
Description

CML Repeater 2.5V/3.3V 167Pin BGA Tray
Documentation

Datasheet

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SN65LVCP114ZJA Specifications

Attribute	Attribute Value

Part Number	SN65LVCP114ZJA
Manufacturer	TI
ChipWorker Part#	CW18852393
Category	Interface IC, Interface Controller
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	167 Pin
Case/Package	NFBGA-167
Supply Voltage (DC)	2.50 V, 3.30 V
Number of Channels	12 Channel
Power Dissipation	3150 mW
Power Consumption	1.40 W
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Power Dissipation (Max)	3150 mW
Supply Voltage	2.375V ~ 3.465V
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Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tray
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
ECCN Code	EAR99

Product Description

The SN65LVCP114 device is an asynchronous, protocol-agnostic, low-latency QUAD mux, linear-redriver optimized for use in systems operating at up to 14.2 Gbps. The device linearly compensates for channel loss in backplane and active-cable applications. The architecture of SN65LVCP114 linear-redriver is designed to work effectively with ASIC or FPGA products implementing digital equalization using decision feedback equalizer (DFE) technology. The SN65LVCP114 mux, linear-redriver preserves the integrity (composition) of the received signal, ensuring optimum DFE and system performance. The SN65LVCP114 provides a low-power mux-demux, linear-redriver solution while at the same time extending the effectiveness of DFE.
SN65LVCP114 is configurable through GPIO or an I2C interface.
A single 2.5-V or 3.3-V power supply supports the operation of the SN65LVCP114.
The SN65LVCP114 is packaged in a 12-mm × 12-mm × 1-mm PBGA package with 0.8-mm pitch.
The SN65LVCP114 has three ports; each port is a quad lane. The switch logic of SN65LVCP114 can be implemented to support a 2:1 MUX per lane, 1:2 DEMUX per lane, and independent lane switching. The receive equalization can be independently programmed for each of the ports. The SN65LVCP114 supports loopback on all three ports.

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